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43a6ec7452
This was originally committed as r255762, but reverted as it broke windows bots. Re-commitiing the exact same patch, as the underlying cause was fixed by r258677. ARMv8.2-A adds 16-bit floating point versions of all existing VFP floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. The assembly for these instructions uses S registers (AArch32 does not have H registers), but the instructions have ".f16" type specifiers rather than ".f32" or ".f64". The top 16 bits of each source register are ignored, and the top 16 bits of the destination register are set to zero. These instructions are mostly the same as the 32- and 64-bit versions, but they use coprocessor 9 rather than 10 and 11. Two new instructions, VMOVX and VINS, have been added to allow packing and extracting two 16-bit floats stored in the top and bottom halves of an S register. New fixup kinds have been added for the PC-relative load and store instructions, but no ELF relocations have been added as they have a range of 512 bytes. Differential Revision: http://reviews.llvm.org/D15038 llvm-svn: 258678
118 lines
4.3 KiB
C++
118 lines
4.3 KiB
C++
//===-- ARMFixupKinds.h - ARM Specific Fixup Entries ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMFIXUPKINDS_H
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#define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMFIXUPKINDS_H
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#include "llvm/MC/MCFixup.h"
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namespace llvm {
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namespace ARM {
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enum Fixups {
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// fixup_arm_ldst_pcrel_12 - 12-bit PC relative relocation for symbol
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// addresses
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fixup_arm_ldst_pcrel_12 = FirstTargetFixupKind,
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// fixup_t2_ldst_pcrel_12 - Equivalent to fixup_arm_ldst_pcrel_12, with
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// the 16-bit halfwords reordered.
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fixup_t2_ldst_pcrel_12,
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// fixup_arm_pcrel_10_unscaled - 10-bit PC relative relocation for symbol
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// addresses used in LDRD/LDRH/LDRB/etc. instructions. All bits are encoded.
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fixup_arm_pcrel_10_unscaled,
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// fixup_arm_pcrel_10 - 10-bit PC relative relocation for symbol addresses
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// used in VFP instructions where the lower 2 bits are not encoded
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// (so it's encoded as an 8-bit immediate).
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fixup_arm_pcrel_10,
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// fixup_t2_pcrel_10 - Equivalent to fixup_arm_pcrel_10, accounting for
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// the short-swapped encoding of Thumb2 instructions.
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fixup_t2_pcrel_10,
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// fixup_arm_pcrel_9 - 9-bit PC relative relocation for symbol addresses
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// used in VFP instructions where bit 0 not encoded (so it's encoded as an
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// 8-bit immediate).
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fixup_arm_pcrel_9,
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// fixup_t2_pcrel_9 - Equivalent to fixup_arm_pcrel_9, accounting for
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// the short-swapped encoding of Thumb2 instructions.
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fixup_t2_pcrel_9,
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// fixup_thumb_adr_pcrel_10 - 10-bit PC relative relocation for symbol
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// addresses where the lower 2 bits are not encoded (so it's encoded as an
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// 8-bit immediate).
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fixup_thumb_adr_pcrel_10,
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// fixup_arm_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
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// instruction.
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fixup_arm_adr_pcrel_12,
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// fixup_t2_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
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// instruction.
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fixup_t2_adr_pcrel_12,
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// fixup_arm_condbranch - 24-bit PC relative relocation for conditional branch
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// instructions.
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fixup_arm_condbranch,
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// fixup_arm_uncondbranch - 24-bit PC relative relocation for
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// branch instructions. (unconditional)
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fixup_arm_uncondbranch,
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// fixup_t2_condbranch - 20-bit PC relative relocation for Thumb2 direct
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// uconditional branch instructions.
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fixup_t2_condbranch,
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// fixup_t2_uncondbranch - 20-bit PC relative relocation for Thumb2 direct
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// branch unconditional branch instructions.
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fixup_t2_uncondbranch,
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// fixup_arm_thumb_br - 12-bit fixup for Thumb B instructions.
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fixup_arm_thumb_br,
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// The following fixups handle the ARM BL instructions. These can be
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// conditionalised; however, the ARM ELF ABI requires a different relocation
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// in that case: R_ARM_JUMP24 instead of R_ARM_CALL. The difference is that
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// R_ARM_CALL is allowed to change the instruction to a BLX inline, which has
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// no conditional version; R_ARM_JUMP24 would have to insert a veneer.
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//
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// MachO does not draw a distinction between the two cases, so it will treat
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// fixup_arm_uncondbl and fixup_arm_condbl as identical fixups.
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// fixup_arm_uncondbl - Fixup for unconditional ARM BL instructions.
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fixup_arm_uncondbl,
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// fixup_arm_condbl - Fixup for ARM BL instructions with nontrivial
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// conditionalisation.
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fixup_arm_condbl,
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// fixup_arm_blx - Fixup for ARM BLX instructions.
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fixup_arm_blx,
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// fixup_arm_thumb_bl - Fixup for Thumb BL instructions.
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fixup_arm_thumb_bl,
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// fixup_arm_thumb_blx - Fixup for Thumb BLX instructions.
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fixup_arm_thumb_blx,
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// fixup_arm_thumb_cb - Fixup for Thumb branch instructions.
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fixup_arm_thumb_cb,
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// fixup_arm_thumb_cp - Fixup for Thumb load/store from constant pool instrs.
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fixup_arm_thumb_cp,
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// fixup_arm_thumb_bcc - Fixup for Thumb conditional branching instructions.
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fixup_arm_thumb_bcc,
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// The next two are for the movt/movw pair
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// the 16bit imm field are split into imm{15-12} and imm{11-0}
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fixup_arm_movt_hi16, // :upper16:
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fixup_arm_movw_lo16, // :lower16:
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fixup_t2_movt_hi16, // :upper16:
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fixup_t2_movw_lo16, // :lower16:
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// Marker
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LastTargetFixupKind,
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NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
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};
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}
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}
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#endif
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