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537 lines
16 KiB
C++
537 lines
16 KiB
C++
//===- HexagonBlockRanges.cpp ---------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonBlockRanges.h"
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#include "HexagonInstrInfo.h"
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#include "HexagonSubtarget.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include <algorithm>
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#include <cassert>
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#include <cstdint>
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#include <iterator>
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#include <map>
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#include <utility>
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using namespace llvm;
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#define DEBUG_TYPE "hbr"
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bool HexagonBlockRanges::IndexRange::overlaps(const IndexRange &A) const {
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// If A contains start(), or "this" contains A.start(), then overlap.
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IndexType S = start(), E = end(), AS = A.start(), AE = A.end();
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if (AS == S)
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return true;
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bool SbAE = (S < AE) || (S == AE && A.TiedEnd); // S-before-AE.
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bool ASbE = (AS < E) || (AS == E && TiedEnd); // AS-before-E.
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if ((AS < S && SbAE) || (S < AS && ASbE))
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return true;
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// Otherwise no overlap.
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return false;
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}
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bool HexagonBlockRanges::IndexRange::contains(const IndexRange &A) const {
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if (start() <= A.start()) {
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// Treat "None" in the range end as equal to the range start.
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IndexType E = (end() != IndexType::None) ? end() : start();
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IndexType AE = (A.end() != IndexType::None) ? A.end() : A.start();
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if (AE <= E)
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return true;
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}
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return false;
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}
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void HexagonBlockRanges::IndexRange::merge(const IndexRange &A) {
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// Allow merging adjacent ranges.
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assert(end() == A.start() || overlaps(A));
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IndexType AS = A.start(), AE = A.end();
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if (AS < start() || start() == IndexType::None)
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setStart(AS);
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if (end() < AE || end() == IndexType::None) {
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setEnd(AE);
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TiedEnd = A.TiedEnd;
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} else {
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if (end() == AE)
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TiedEnd |= A.TiedEnd;
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}
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if (A.Fixed)
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Fixed = true;
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}
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void HexagonBlockRanges::RangeList::include(const RangeList &RL) {
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for (auto &R : RL)
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if (!is_contained(*this, R))
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push_back(R);
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}
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// Merge all overlapping ranges in the list, so that all that remains
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// is a list of disjoint ranges.
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void HexagonBlockRanges::RangeList::unionize(bool MergeAdjacent) {
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if (empty())
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return;
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llvm::sort(begin(), end());
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iterator Iter = begin();
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while (Iter != end()-1) {
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iterator Next = std::next(Iter);
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// If MergeAdjacent is true, merge ranges A and B, where A.end == B.start.
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// This allows merging dead ranges, but is not valid for live ranges.
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bool Merge = MergeAdjacent && (Iter->end() == Next->start());
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if (Merge || Iter->overlaps(*Next)) {
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Iter->merge(*Next);
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erase(Next);
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continue;
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}
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++Iter;
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}
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}
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// Compute a range A-B and add it to the list.
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void HexagonBlockRanges::RangeList::addsub(const IndexRange &A,
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const IndexRange &B) {
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// Exclusion of non-overlapping ranges makes some checks simpler
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// later in this function.
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if (!A.overlaps(B)) {
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// A - B = A.
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add(A);
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return;
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}
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IndexType AS = A.start(), AE = A.end();
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IndexType BS = B.start(), BE = B.end();
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// If AE is None, then A is included in B, since A and B overlap.
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// The result of subtraction if empty, so just return.
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if (AE == IndexType::None)
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return;
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if (AS < BS) {
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// A starts before B.
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// AE cannot be None since A and B overlap.
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assert(AE != IndexType::None);
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// Add the part of A that extends on the "less" side of B.
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add(AS, BS, A.Fixed, false);
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}
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if (BE < AE) {
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// BE cannot be Exit here.
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if (BE == IndexType::None)
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add(BS, AE, A.Fixed, false);
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else
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add(BE, AE, A.Fixed, false);
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}
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}
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// Subtract a given range from each element in the list.
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void HexagonBlockRanges::RangeList::subtract(const IndexRange &Range) {
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// Cannot assume that the list is unionized (i.e. contains only non-
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// overlapping ranges.
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RangeList T;
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for (iterator Next, I = begin(); I != end(); I = Next) {
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IndexRange &Rg = *I;
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if (Rg.overlaps(Range)) {
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T.addsub(Rg, Range);
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Next = this->erase(I);
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} else {
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Next = std::next(I);
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}
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}
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include(T);
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}
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HexagonBlockRanges::InstrIndexMap::InstrIndexMap(MachineBasicBlock &B)
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: Block(B) {
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IndexType Idx = IndexType::First;
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First = Idx;
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for (auto &In : B) {
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if (In.isDebugInstr())
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continue;
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assert(getIndex(&In) == IndexType::None && "Instruction already in map");
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Map.insert(std::make_pair(Idx, &In));
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++Idx;
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}
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Last = B.empty() ? IndexType::None : unsigned(Idx)-1;
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}
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MachineInstr *HexagonBlockRanges::InstrIndexMap::getInstr(IndexType Idx) const {
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auto F = Map.find(Idx);
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return (F != Map.end()) ? F->second : nullptr;
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}
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HexagonBlockRanges::IndexType HexagonBlockRanges::InstrIndexMap::getIndex(
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MachineInstr *MI) const {
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for (auto &I : Map)
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if (I.second == MI)
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return I.first;
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return IndexType::None;
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}
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HexagonBlockRanges::IndexType HexagonBlockRanges::InstrIndexMap::getPrevIndex(
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IndexType Idx) const {
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assert (Idx != IndexType::None);
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if (Idx == IndexType::Entry)
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return IndexType::None;
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if (Idx == IndexType::Exit)
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return Last;
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if (Idx == First)
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return IndexType::Entry;
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return unsigned(Idx)-1;
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}
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HexagonBlockRanges::IndexType HexagonBlockRanges::InstrIndexMap::getNextIndex(
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IndexType Idx) const {
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assert (Idx != IndexType::None);
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if (Idx == IndexType::Entry)
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return IndexType::First;
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if (Idx == IndexType::Exit || Idx == Last)
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return IndexType::None;
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return unsigned(Idx)+1;
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}
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void HexagonBlockRanges::InstrIndexMap::replaceInstr(MachineInstr *OldMI,
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MachineInstr *NewMI) {
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for (auto &I : Map) {
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if (I.second != OldMI)
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continue;
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if (NewMI != nullptr)
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I.second = NewMI;
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else
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Map.erase(I.first);
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break;
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}
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}
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HexagonBlockRanges::HexagonBlockRanges(MachineFunction &mf)
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: MF(mf), HST(mf.getSubtarget<HexagonSubtarget>()),
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TII(*HST.getInstrInfo()), TRI(*HST.getRegisterInfo()),
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Reserved(TRI.getReservedRegs(mf)) {
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// Consider all non-allocatable registers as reserved.
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for (const TargetRegisterClass *RC : TRI.regclasses()) {
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if (RC->isAllocatable())
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continue;
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for (unsigned R : *RC)
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Reserved[R] = true;
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}
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}
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HexagonBlockRanges::RegisterSet HexagonBlockRanges::getLiveIns(
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const MachineBasicBlock &B, const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI) {
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RegisterSet LiveIns;
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RegisterSet Tmp;
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for (auto I : B.liveins()) {
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MCSubRegIndexIterator S(I.PhysReg, &TRI);
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if (I.LaneMask.all() || (I.LaneMask.any() && !S.isValid())) {
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Tmp.insert({I.PhysReg, 0});
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continue;
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}
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for (; S.isValid(); ++S) {
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unsigned SI = S.getSubRegIndex();
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if ((I.LaneMask & TRI.getSubRegIndexLaneMask(SI)).any())
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Tmp.insert({S.getSubReg(), 0});
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}
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}
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for (auto R : Tmp) {
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if (!Reserved[R.Reg])
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LiveIns.insert(R);
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for (auto S : expandToSubRegs(R, MRI, TRI))
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if (!Reserved[S.Reg])
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LiveIns.insert(S);
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}
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return LiveIns;
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}
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HexagonBlockRanges::RegisterSet HexagonBlockRanges::expandToSubRegs(
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RegisterRef R, const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI) {
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RegisterSet SRs;
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if (R.Sub != 0) {
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SRs.insert(R);
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return SRs;
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}
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if (TargetRegisterInfo::isPhysicalRegister(R.Reg)) {
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MCSubRegIterator I(R.Reg, &TRI);
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if (!I.isValid())
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SRs.insert({R.Reg, 0});
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for (; I.isValid(); ++I)
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SRs.insert({*I, 0});
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} else {
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assert(TargetRegisterInfo::isVirtualRegister(R.Reg));
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auto &RC = *MRI.getRegClass(R.Reg);
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unsigned PReg = *RC.begin();
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MCSubRegIndexIterator I(PReg, &TRI);
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if (!I.isValid())
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SRs.insert({R.Reg, 0});
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for (; I.isValid(); ++I)
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SRs.insert({R.Reg, I.getSubRegIndex()});
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}
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return SRs;
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}
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void HexagonBlockRanges::computeInitialLiveRanges(InstrIndexMap &IndexMap,
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RegToRangeMap &LiveMap) {
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std::map<RegisterRef,IndexType> LastDef, LastUse;
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RegisterSet LiveOnEntry;
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MachineBasicBlock &B = IndexMap.getBlock();
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MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
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for (auto R : getLiveIns(B, MRI, TRI))
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LiveOnEntry.insert(R);
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for (auto R : LiveOnEntry)
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LastDef[R] = IndexType::Entry;
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auto closeRange = [&LastUse,&LastDef,&LiveMap] (RegisterRef R) -> void {
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auto LD = LastDef[R], LU = LastUse[R];
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if (LD == IndexType::None)
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LD = IndexType::Entry;
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if (LU == IndexType::None)
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LU = IndexType::Exit;
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LiveMap[R].add(LD, LU, false, false);
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LastUse[R] = LastDef[R] = IndexType::None;
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};
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RegisterSet Defs, Clobbers;
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for (auto &In : B) {
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if (In.isDebugInstr())
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continue;
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IndexType Index = IndexMap.getIndex(&In);
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// Process uses first.
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for (auto &Op : In.operands()) {
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if (!Op.isReg() || !Op.isUse() || Op.isUndef())
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continue;
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RegisterRef R = { Op.getReg(), Op.getSubReg() };
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if (TargetRegisterInfo::isPhysicalRegister(R.Reg) && Reserved[R.Reg])
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continue;
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bool IsKill = Op.isKill();
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for (auto S : expandToSubRegs(R, MRI, TRI)) {
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LastUse[S] = Index;
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if (IsKill)
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closeRange(S);
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}
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}
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// Process defs and clobbers.
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Defs.clear();
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Clobbers.clear();
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for (auto &Op : In.operands()) {
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if (!Op.isReg() || !Op.isDef() || Op.isUndef())
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continue;
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RegisterRef R = { Op.getReg(), Op.getSubReg() };
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for (auto S : expandToSubRegs(R, MRI, TRI)) {
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if (TargetRegisterInfo::isPhysicalRegister(S.Reg) && Reserved[S.Reg])
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continue;
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if (Op.isDead())
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Clobbers.insert(S);
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else
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Defs.insert(S);
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}
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}
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for (auto &Op : In.operands()) {
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if (!Op.isRegMask())
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continue;
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const uint32_t *BM = Op.getRegMask();
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for (unsigned PR = 1, N = TRI.getNumRegs(); PR != N; ++PR) {
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// Skip registers that have subregisters. A register is preserved
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// iff its bit is set in the regmask, so if R1:0 was preserved, both
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// R1 and R0 would also be present.
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if (MCSubRegIterator(PR, &TRI, false).isValid())
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continue;
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if (Reserved[PR])
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continue;
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if (BM[PR/32] & (1u << (PR%32)))
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continue;
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RegisterRef R = { PR, 0 };
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if (!Defs.count(R))
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Clobbers.insert(R);
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}
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}
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// Defs and clobbers can overlap, e.g.
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// dead %d0 = COPY %5, implicit-def %r0, implicit-def %r1
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for (RegisterRef R : Defs)
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Clobbers.erase(R);
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// Update maps for defs.
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for (RegisterRef S : Defs) {
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// Defs should already be expanded into subregs.
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assert(!TargetRegisterInfo::isPhysicalRegister(S.Reg) ||
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!MCSubRegIterator(S.Reg, &TRI, false).isValid());
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if (LastDef[S] != IndexType::None || LastUse[S] != IndexType::None)
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closeRange(S);
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LastDef[S] = Index;
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}
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// Update maps for clobbers.
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for (RegisterRef S : Clobbers) {
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// Clobbers should already be expanded into subregs.
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assert(!TargetRegisterInfo::isPhysicalRegister(S.Reg) ||
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!MCSubRegIterator(S.Reg, &TRI, false).isValid());
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if (LastDef[S] != IndexType::None || LastUse[S] != IndexType::None)
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closeRange(S);
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// Create a single-instruction range.
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LastDef[S] = LastUse[S] = Index;
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closeRange(S);
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}
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}
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// Collect live-on-exit.
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RegisterSet LiveOnExit;
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for (auto *SB : B.successors())
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for (auto R : getLiveIns(*SB, MRI, TRI))
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LiveOnExit.insert(R);
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for (auto R : LiveOnExit)
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LastUse[R] = IndexType::Exit;
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// Process remaining registers.
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RegisterSet Left;
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for (auto &I : LastUse)
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if (I.second != IndexType::None)
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Left.insert(I.first);
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for (auto &I : LastDef)
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if (I.second != IndexType::None)
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Left.insert(I.first);
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for (auto R : Left)
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closeRange(R);
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// Finalize the live ranges.
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for (auto &P : LiveMap)
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P.second.unionize();
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}
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HexagonBlockRanges::RegToRangeMap HexagonBlockRanges::computeLiveMap(
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InstrIndexMap &IndexMap) {
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RegToRangeMap LiveMap;
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LLVM_DEBUG(dbgs() << __func__ << ": index map\n" << IndexMap << '\n');
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computeInitialLiveRanges(IndexMap, LiveMap);
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LLVM_DEBUG(dbgs() << __func__ << ": live map\n"
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<< PrintRangeMap(LiveMap, TRI) << '\n');
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return LiveMap;
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}
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HexagonBlockRanges::RegToRangeMap HexagonBlockRanges::computeDeadMap(
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InstrIndexMap &IndexMap, RegToRangeMap &LiveMap) {
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RegToRangeMap DeadMap;
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auto addDeadRanges = [&IndexMap,&LiveMap,&DeadMap] (RegisterRef R) -> void {
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auto F = LiveMap.find(R);
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if (F == LiveMap.end() || F->second.empty()) {
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DeadMap[R].add(IndexType::Entry, IndexType::Exit, false, false);
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return;
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}
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RangeList &RL = F->second;
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RangeList::iterator A = RL.begin(), Z = RL.end()-1;
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// Try to create the initial range.
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if (A->start() != IndexType::Entry) {
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IndexType DE = IndexMap.getPrevIndex(A->start());
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if (DE != IndexType::Entry)
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DeadMap[R].add(IndexType::Entry, DE, false, false);
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}
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while (A != Z) {
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// Creating a dead range that follows A. Pay attention to empty
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// ranges (i.e. those ending with "None").
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IndexType AE = (A->end() == IndexType::None) ? A->start() : A->end();
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IndexType DS = IndexMap.getNextIndex(AE);
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++A;
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IndexType DE = IndexMap.getPrevIndex(A->start());
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if (DS < DE)
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DeadMap[R].add(DS, DE, false, false);
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}
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// Try to create the final range.
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if (Z->end() != IndexType::Exit) {
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IndexType ZE = (Z->end() == IndexType::None) ? Z->start() : Z->end();
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IndexType DS = IndexMap.getNextIndex(ZE);
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if (DS < IndexType::Exit)
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DeadMap[R].add(DS, IndexType::Exit, false, false);
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}
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};
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MachineFunction &MF = *IndexMap.getBlock().getParent();
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auto &MRI = MF.getRegInfo();
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unsigned NumRegs = TRI.getNumRegs();
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BitVector Visited(NumRegs);
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for (unsigned R = 1; R < NumRegs; ++R) {
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for (auto S : expandToSubRegs({R,0}, MRI, TRI)) {
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if (Reserved[S.Reg] || Visited[S.Reg])
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continue;
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addDeadRanges(S);
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Visited[S.Reg] = true;
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}
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}
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for (auto &P : LiveMap)
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if (TargetRegisterInfo::isVirtualRegister(P.first.Reg))
|
|
addDeadRanges(P.first);
|
|
|
|
LLVM_DEBUG(dbgs() << __func__ << ": dead map\n"
|
|
<< PrintRangeMap(DeadMap, TRI) << '\n');
|
|
return DeadMap;
|
|
}
|
|
|
|
raw_ostream &llvm::operator<<(raw_ostream &OS,
|
|
HexagonBlockRanges::IndexType Idx) {
|
|
if (Idx == HexagonBlockRanges::IndexType::None)
|
|
return OS << '-';
|
|
if (Idx == HexagonBlockRanges::IndexType::Entry)
|
|
return OS << 'n';
|
|
if (Idx == HexagonBlockRanges::IndexType::Exit)
|
|
return OS << 'x';
|
|
return OS << unsigned(Idx)-HexagonBlockRanges::IndexType::First+1;
|
|
}
|
|
|
|
// A mapping to translate between instructions and their indices.
|
|
raw_ostream &llvm::operator<<(raw_ostream &OS,
|
|
const HexagonBlockRanges::IndexRange &IR) {
|
|
OS << '[' << IR.start() << ':' << IR.end() << (IR.TiedEnd ? '}' : ']');
|
|
if (IR.Fixed)
|
|
OS << '!';
|
|
return OS;
|
|
}
|
|
|
|
raw_ostream &llvm::operator<<(raw_ostream &OS,
|
|
const HexagonBlockRanges::RangeList &RL) {
|
|
for (auto &R : RL)
|
|
OS << R << " ";
|
|
return OS;
|
|
}
|
|
|
|
raw_ostream &llvm::operator<<(raw_ostream &OS,
|
|
const HexagonBlockRanges::InstrIndexMap &M) {
|
|
for (auto &In : M.Block) {
|
|
HexagonBlockRanges::IndexType Idx = M.getIndex(&In);
|
|
OS << Idx << (Idx == M.Last ? ". " : " ") << In;
|
|
}
|
|
return OS;
|
|
}
|
|
|
|
raw_ostream &llvm::operator<<(raw_ostream &OS,
|
|
const HexagonBlockRanges::PrintRangeMap &P) {
|
|
for (auto &I : P.Map) {
|
|
const HexagonBlockRanges::RangeList &RL = I.second;
|
|
OS << printReg(I.first.Reg, &P.TRI, I.first.Sub) << " -> " << RL << "\n";
|
|
}
|
|
return OS;
|
|
}
|