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381 lines
11 KiB
C++
381 lines
11 KiB
C++
//===- RDFRegisters.cpp ---------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "RDFRegisters.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/MC/LaneBitmask.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <cstdint>
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#include <set>
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#include <utility>
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using namespace llvm;
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using namespace rdf;
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PhysicalRegisterInfo::PhysicalRegisterInfo(const TargetRegisterInfo &tri,
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const MachineFunction &mf)
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: TRI(tri) {
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RegInfos.resize(TRI.getNumRegs());
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BitVector BadRC(TRI.getNumRegs());
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for (const TargetRegisterClass *RC : TRI.regclasses()) {
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for (MCPhysReg R : *RC) {
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RegInfo &RI = RegInfos[R];
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if (RI.RegClass != nullptr && !BadRC[R]) {
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if (RC->LaneMask != RI.RegClass->LaneMask) {
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BadRC.set(R);
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RI.RegClass = nullptr;
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}
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} else
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RI.RegClass = RC;
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}
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}
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UnitInfos.resize(TRI.getNumRegUnits());
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for (uint32_t U = 0, NU = TRI.getNumRegUnits(); U != NU; ++U) {
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if (UnitInfos[U].Reg != 0)
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continue;
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MCRegUnitRootIterator R(U, &TRI);
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assert(R.isValid());
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RegisterId F = *R;
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++R;
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if (R.isValid()) {
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UnitInfos[U].Mask = LaneBitmask::getAll();
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UnitInfos[U].Reg = F;
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} else {
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for (MCRegUnitMaskIterator I(F, &TRI); I.isValid(); ++I) {
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std::pair<uint32_t,LaneBitmask> P = *I;
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UnitInfo &UI = UnitInfos[P.first];
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UI.Reg = F;
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if (P.second.any()) {
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UI.Mask = P.second;
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} else {
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if (const TargetRegisterClass *RC = RegInfos[F].RegClass)
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UI.Mask = RC->LaneMask;
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else
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UI.Mask = LaneBitmask::getAll();
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}
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}
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}
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}
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for (const uint32_t *RM : TRI.getRegMasks())
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RegMasks.insert(RM);
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for (const MachineBasicBlock &B : mf)
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for (const MachineInstr &In : B)
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for (const MachineOperand &Op : In.operands())
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if (Op.isRegMask())
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RegMasks.insert(Op.getRegMask());
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MaskInfos.resize(RegMasks.size()+1);
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for (uint32_t M = 1, NM = RegMasks.size(); M <= NM; ++M) {
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BitVector PU(TRI.getNumRegUnits());
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const uint32_t *MB = RegMasks.get(M);
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for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i) {
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if (!(MB[i/32] & (1u << (i%32))))
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continue;
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for (MCRegUnitIterator U(i, &TRI); U.isValid(); ++U)
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PU.set(*U);
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}
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MaskInfos[M].Units = PU.flip();
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}
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}
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RegisterRef PhysicalRegisterInfo::normalize(RegisterRef RR) const {
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return RR;
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}
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std::set<RegisterId> PhysicalRegisterInfo::getAliasSet(RegisterId Reg) const {
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// Do not include RR in the alias set.
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std::set<RegisterId> AS;
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assert(isRegMaskId(Reg) || TargetRegisterInfo::isPhysicalRegister(Reg));
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if (isRegMaskId(Reg)) {
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// XXX SLOW
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const uint32_t *MB = getRegMaskBits(Reg);
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for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i) {
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if (MB[i/32] & (1u << (i%32)))
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continue;
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AS.insert(i);
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}
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for (const uint32_t *RM : RegMasks) {
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RegisterId MI = getRegMaskId(RM);
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if (MI != Reg && aliasMM(RegisterRef(Reg), RegisterRef(MI)))
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AS.insert(MI);
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}
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return AS;
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}
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for (MCRegAliasIterator AI(Reg, &TRI, false); AI.isValid(); ++AI)
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AS.insert(*AI);
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for (const uint32_t *RM : RegMasks) {
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RegisterId MI = getRegMaskId(RM);
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if (aliasRM(RegisterRef(Reg), RegisterRef(MI)))
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AS.insert(MI);
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}
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return AS;
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}
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bool PhysicalRegisterInfo::aliasRR(RegisterRef RA, RegisterRef RB) const {
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assert(TargetRegisterInfo::isPhysicalRegister(RA.Reg));
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assert(TargetRegisterInfo::isPhysicalRegister(RB.Reg));
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MCRegUnitMaskIterator UMA(RA.Reg, &TRI);
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MCRegUnitMaskIterator UMB(RB.Reg, &TRI);
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// Reg units are returned in the numerical order.
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while (UMA.isValid() && UMB.isValid()) {
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// Skip units that are masked off in RA.
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std::pair<RegisterId,LaneBitmask> PA = *UMA;
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if (PA.second.any() && (PA.second & RA.Mask).none()) {
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++UMA;
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continue;
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}
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// Skip units that are masked off in RB.
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std::pair<RegisterId,LaneBitmask> PB = *UMB;
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if (PB.second.any() && (PB.second & RB.Mask).none()) {
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++UMB;
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continue;
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}
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if (PA.first == PB.first)
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return true;
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if (PA.first < PB.first)
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++UMA;
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else if (PB.first < PA.first)
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++UMB;
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}
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return false;
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}
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bool PhysicalRegisterInfo::aliasRM(RegisterRef RR, RegisterRef RM) const {
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assert(TargetRegisterInfo::isPhysicalRegister(RR.Reg) && isRegMaskId(RM.Reg));
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const uint32_t *MB = getRegMaskBits(RM.Reg);
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bool Preserved = MB[RR.Reg/32] & (1u << (RR.Reg%32));
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// If the lane mask information is "full", e.g. when the given lane mask
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// is a superset of the lane mask from the register class, check the regmask
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// bit directly.
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if (RR.Mask == LaneBitmask::getAll())
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return !Preserved;
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const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass;
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if (RC != nullptr && (RR.Mask & RC->LaneMask) == RC->LaneMask)
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return !Preserved;
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// Otherwise, check all subregisters whose lane mask overlaps the given
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// mask. For each such register, if it is preserved by the regmask, then
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// clear the corresponding bits in the given mask. If at the end, all
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// bits have been cleared, the register does not alias the regmask (i.e.
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// is it preserved by it).
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LaneBitmask M = RR.Mask;
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for (MCSubRegIndexIterator SI(RR.Reg, &TRI); SI.isValid(); ++SI) {
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LaneBitmask SM = TRI.getSubRegIndexLaneMask(SI.getSubRegIndex());
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if ((SM & RR.Mask).none())
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continue;
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unsigned SR = SI.getSubReg();
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if (!(MB[SR/32] & (1u << (SR%32))))
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continue;
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// The subregister SR is preserved.
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M &= ~SM;
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if (M.none())
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return false;
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}
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return true;
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}
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bool PhysicalRegisterInfo::aliasMM(RegisterRef RM, RegisterRef RN) const {
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assert(isRegMaskId(RM.Reg) && isRegMaskId(RN.Reg));
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unsigned NumRegs = TRI.getNumRegs();
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const uint32_t *BM = getRegMaskBits(RM.Reg);
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const uint32_t *BN = getRegMaskBits(RN.Reg);
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for (unsigned w = 0, nw = NumRegs/32; w != nw; ++w) {
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// Intersect the negations of both words. Disregard reg=0,
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// i.e. 0th bit in the 0th word.
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uint32_t C = ~BM[w] & ~BN[w];
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if (w == 0)
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C &= ~1;
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if (C)
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return true;
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}
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// Check the remaining registers in the last word.
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unsigned TailRegs = NumRegs % 32;
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if (TailRegs == 0)
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return false;
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unsigned TW = NumRegs / 32;
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uint32_t TailMask = (1u << TailRegs) - 1;
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if (~BM[TW] & ~BN[TW] & TailMask)
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return true;
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return false;
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}
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RegisterRef PhysicalRegisterInfo::mapTo(RegisterRef RR, unsigned R) const {
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if (RR.Reg == R)
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return RR;
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if (unsigned Idx = TRI.getSubRegIndex(R, RR.Reg))
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return RegisterRef(R, TRI.composeSubRegIndexLaneMask(Idx, RR.Mask));
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if (unsigned Idx = TRI.getSubRegIndex(RR.Reg, R)) {
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const RegInfo &RI = RegInfos[R];
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LaneBitmask RCM = RI.RegClass ? RI.RegClass->LaneMask
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: LaneBitmask::getAll();
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LaneBitmask M = TRI.reverseComposeSubRegIndexLaneMask(Idx, RR.Mask);
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return RegisterRef(R, M & RCM);
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}
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llvm_unreachable("Invalid arguments: unrelated registers?");
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}
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bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
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if (PhysicalRegisterInfo::isRegMaskId(RR.Reg))
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return Units.anyCommon(PRI.getMaskUnits(RR.Reg));
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for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
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std::pair<uint32_t,LaneBitmask> P = *U;
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if (P.second.none() || (P.second & RR.Mask).any())
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if (Units.test(P.first))
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return true;
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}
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return false;
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}
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bool RegisterAggr::hasCoverOf(RegisterRef RR) const {
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if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) {
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BitVector T(PRI.getMaskUnits(RR.Reg));
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return T.reset(Units).none();
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}
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for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
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std::pair<uint32_t,LaneBitmask> P = *U;
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if (P.second.none() || (P.second & RR.Mask).any())
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if (!Units.test(P.first))
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return false;
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}
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return true;
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}
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RegisterAggr &RegisterAggr::insert(RegisterRef RR) {
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if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) {
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Units |= PRI.getMaskUnits(RR.Reg);
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return *this;
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}
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for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
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std::pair<uint32_t,LaneBitmask> P = *U;
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if (P.second.none() || (P.second & RR.Mask).any())
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Units.set(P.first);
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}
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return *this;
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}
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RegisterAggr &RegisterAggr::insert(const RegisterAggr &RG) {
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Units |= RG.Units;
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return *this;
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}
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RegisterAggr &RegisterAggr::intersect(RegisterRef RR) {
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return intersect(RegisterAggr(PRI).insert(RR));
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}
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RegisterAggr &RegisterAggr::intersect(const RegisterAggr &RG) {
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Units &= RG.Units;
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return *this;
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}
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RegisterAggr &RegisterAggr::clear(RegisterRef RR) {
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return clear(RegisterAggr(PRI).insert(RR));
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}
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RegisterAggr &RegisterAggr::clear(const RegisterAggr &RG) {
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Units.reset(RG.Units);
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return *this;
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}
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RegisterRef RegisterAggr::intersectWith(RegisterRef RR) const {
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RegisterAggr T(PRI);
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T.insert(RR).intersect(*this);
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if (T.empty())
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return RegisterRef();
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RegisterRef NR = T.makeRegRef();
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assert(NR);
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return NR;
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}
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RegisterRef RegisterAggr::clearIn(RegisterRef RR) const {
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return RegisterAggr(PRI).insert(RR).clear(*this).makeRegRef();
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}
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RegisterRef RegisterAggr::makeRegRef() const {
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int U = Units.find_first();
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if (U < 0)
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return RegisterRef();
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auto AliasedRegs = [this] (uint32_t Unit, BitVector &Regs) {
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for (MCRegUnitRootIterator R(Unit, &PRI.getTRI()); R.isValid(); ++R)
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for (MCSuperRegIterator S(*R, &PRI.getTRI(), true); S.isValid(); ++S)
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Regs.set(*S);
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};
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// Find the set of all registers that are aliased to all the units
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// in this aggregate.
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// Get all the registers aliased to the first unit in the bit vector.
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BitVector Regs(PRI.getTRI().getNumRegs());
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AliasedRegs(U, Regs);
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U = Units.find_next(U);
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// For each other unit, intersect it with the set of all registers
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// aliased that unit.
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while (U >= 0) {
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BitVector AR(PRI.getTRI().getNumRegs());
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AliasedRegs(U, AR);
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Regs &= AR;
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U = Units.find_next(U);
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}
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// If there is at least one register remaining, pick the first one,
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// and consolidate the masks of all of its units contained in this
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// aggregate.
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int F = Regs.find_first();
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if (F <= 0)
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return RegisterRef();
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LaneBitmask M;
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for (MCRegUnitMaskIterator I(F, &PRI.getTRI()); I.isValid(); ++I) {
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std::pair<uint32_t,LaneBitmask> P = *I;
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if (Units.test(P.first))
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M |= P.second.none() ? LaneBitmask::getAll() : P.second;
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}
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return RegisterRef(F, M);
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}
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void RegisterAggr::print(raw_ostream &OS) const {
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OS << '{';
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for (int U = Units.find_first(); U >= 0; U = Units.find_next(U))
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OS << ' ' << printRegUnit(U, &PRI.getTRI());
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OS << " }";
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}
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RegisterAggr::rr_iterator::rr_iterator(const RegisterAggr &RG,
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bool End)
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: Owner(&RG) {
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for (int U = RG.Units.find_first(); U >= 0; U = RG.Units.find_next(U)) {
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RegisterRef R = RG.PRI.getRefForUnit(U);
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Masks[R.Reg] |= R.Mask;
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}
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Pos = End ? Masks.end() : Masks.begin();
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Index = End ? Masks.size() : 0;
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}
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