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184 lines
7.7 KiB
C++
184 lines
7.7 KiB
C++
//===-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that MSP430 uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H
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#define LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H
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#include "MSP430.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetLowering.h"
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namespace llvm {
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namespace MSP430ISD {
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enum NodeType : unsigned {
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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/// Return with a flag operand. Operand 0 is the chain operand.
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RET_FLAG,
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/// Same as RET_FLAG, but used for returning from ISRs.
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RETI_FLAG,
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/// Y = R{R,L}A X, rotate right (left) arithmetically
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RRA, RLA,
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/// Y = RRC X, rotate right via carry
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RRC,
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/// Rotate right via carry, carry gets cleared beforehand by clrc
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RRCL,
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/// CALL - These operations represent an abstract call
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/// instruction, which includes a bunch of information.
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CALL,
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/// Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
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/// and TargetGlobalAddress.
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Wrapper,
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/// CMP - Compare instruction.
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CMP,
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/// SetCC - Operand 0 is condition code, and operand 1 is the flag
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/// operand produced by a CMP instruction.
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SETCC,
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/// MSP430 conditional branches. Operand 0 is the chain operand, operand 1
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/// is the block to branch if condition is true, operand 2 is the
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/// condition code, and operand 3 is the flag operand produced by a CMP
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/// instruction.
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BR_CC,
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/// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
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/// is condition code and operand 4 is flag operand.
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SELECT_CC,
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/// DADD - Decimal addition with carry
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/// TODO Nothing generates a node of this type yet.
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DADD,
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};
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}
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class MSP430Subtarget;
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class MSP430TargetLowering : public TargetLowering {
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public:
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explicit MSP430TargetLowering(const TargetMachine &TM,
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const MSP430Subtarget &STI);
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MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
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return MVT::i8;
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}
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/// LowerOperation - Provide custom lowering hooks for some operations.
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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/// getTargetNodeName - This method returns the name of a target specific
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/// DAG node.
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const char *getTargetNodeName(unsigned Opcode) const override;
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SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
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TargetLowering::ConstraintType
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getConstraintType(StringRef Constraint) const override;
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint, MVT VT) const override;
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/// isTruncateFree - Return true if it's free to truncate a value of type
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/// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in
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/// register R15W to i8 by referencing its sub-register R15B.
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bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
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bool isTruncateFree(EVT VT1, EVT VT2) const override;
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/// isZExtFree - Return true if any actual instruction that defines a value
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/// of type Ty1 implicit zero-extends the value to Ty2 in the result
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/// register. This does not necessarily include registers defined in unknown
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/// ways, such as incoming arguments, or copies from unknown virtual
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/// registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not
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/// necessarily apply to truncate instructions. e.g. on msp430, all
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/// instructions that define 8-bit values implicit zero-extend the result
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/// out to 16 bits.
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bool isZExtFree(Type *Ty1, Type *Ty2) const override;
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bool isZExtFree(EVT VT1, EVT VT2) const override;
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bool isZExtFree(SDValue Val, EVT VT2) const override;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *BB) const override;
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MachineBasicBlock *EmitShiftInstr(MachineInstr &MI,
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MachineBasicBlock *BB) const;
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private:
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SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
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CallingConv::ID CallConv, bool isVarArg,
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bool isTailCall,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue
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LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue
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LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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bool CanLowerReturn(CallingConv::ID CallConv,
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MachineFunction &MF,
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bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SDLoc &dl, SelectionDAG &DAG) const override;
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bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
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SDValue &Base,
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SDValue &Offset,
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ISD::MemIndexedMode &AM,
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SelectionDAG &DAG) const override;
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};
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} // namespace llvm
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#endif
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