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5e921518f7
Occasionally DAGCombiner can spot that a SETCC operation is completely redundant and reduce it to "all true" or "all false". If this happens to a vector, the value produced has to take account of what a normal comparison would have produced, which may be an all-1s bitmask. The fix in SelectionDAG.cpp is tested, however, as far as I can see the code in TargetLowering.cpp is possibly unreachable and almost certainly irrelevant when triggered so there are no tests. However, I believe it's still clearly the right change and may save someone else some hassle if it suddenly becomes reachable. So I'm doing it anyway. llvm-svn: 190147
188 lines
5.4 KiB
LLVM
188 lines
5.4 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=sse2 | FileCheck %s -check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=sse4.1 | FileCheck %s -check-prefix=SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=avx | FileCheck %s -check-prefix=AVX
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define <16 x i8> @v16i8_icmp_uge(<16 x i8> %a, <16 x i8> %b) nounwind readnone ssp uwtable {
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%1 = icmp uge <16 x i8> %a, %b
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%2 = sext <16 x i1> %1 to <16 x i8>
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ret <16 x i8> %2
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; SSE2-LABEL: v16i8_icmp_uge:
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; SSE2: pmaxub %xmm0, %xmm1
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; SSE2: pcmpeqb %xmm1, %xmm0
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; SSE41-LABEL: v16i8_icmp_uge:
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; SSE41: pmaxub %xmm0, %xmm1
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; SSE41: pcmpeqb %xmm1, %xmm0
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; AVX-LABEL: v16i8_icmp_uge:
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; AVX: vpmaxub %xmm1, %xmm0, %xmm1
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; AVX: vpcmpeqb %xmm1, %xmm0, %xmm0
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}
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define <16 x i8> @v16i8_icmp_ule(<16 x i8> %a, <16 x i8> %b) nounwind readnone ssp uwtable {
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%1 = icmp ule <16 x i8> %a, %b
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%2 = sext <16 x i1> %1 to <16 x i8>
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ret <16 x i8> %2
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; SSE2-LABEL: v16i8_icmp_ule:
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; SSE2: pminub %xmm0, %xmm1
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; SSE2: pcmpeqb %xmm1, %xmm0
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; SSE41-LABEL: v16i8_icmp_ule:
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; SSE41: pminub %xmm0, %xmm1
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; SSE41: pcmpeqb %xmm1, %xmm0
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; AVX-LABEL: v16i8_icmp_ule:
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; AVX: vpminub %xmm1, %xmm0, %xmm1
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; AVX: vpcmpeqb %xmm1, %xmm0, %xmm0
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}
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define <8 x i16> @v8i16_icmp_uge(<8 x i16> %a, <8 x i16> %b) nounwind readnone ssp uwtable {
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%1 = icmp uge <8 x i16> %a, %b
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%2 = sext <8 x i1> %1 to <8 x i16>
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ret <8 x i16> %2
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; SSE2-LABEL: v8i16_icmp_uge:
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; SSE2: movdqa {{.*}}(%rip), %xmm2
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; SEE2: pxor %xmm2, %xmm0
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; SSE2: pxor %xmm1, %xmm2
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; SSE2: pcmpgtw %xmm0, %xmm2
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; SSE2: pcmpeqd %xmm0, %xmm0
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; SSE2: pxor %xmm2, %xmm0
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; SSE41-LABEL: v8i16_icmp_uge:
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; SSE41: pmaxuw %xmm0, %xmm1
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; SSE41: pcmpeqw %xmm1, %xmm0
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; AVX-LABEL: v8i16_icmp_uge:
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; AVX: vpmaxuw %xmm1, %xmm0, %xmm1
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; AVX: vpcmpeqw %xmm1, %xmm0, %xmm0
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}
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define <8 x i16> @v8i16_icmp_ule(<8 x i16> %a, <8 x i16> %b) nounwind readnone ssp uwtable {
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%1 = icmp ule <8 x i16> %a, %b
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%2 = sext <8 x i1> %1 to <8 x i16>
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ret <8 x i16> %2
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; SSE2-LABEL: v8i16_icmp_ule:
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; SSE2: movdqa {{.*}}(%rip), %xmm2
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; SSE2: pxor %xmm2, %xmm1
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; SSE2: pxor %xmm2, %xmm0
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; SSE2: pcmpgtw %xmm1, %xmm0
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; SSE2: pcmpeqd %xmm1, %xmm1
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; SSE2: pxor %xmm0, %xmm1
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; SSE2: movdqa %xmm1, %xmm0
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; SSE41-LABEL: v8i16_icmp_ule:
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; SSE41: pminuw %xmm0, %xmm1
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; SSE41: pcmpeqw %xmm1, %xmm0
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; AVX-LABEL: v8i16_icmp_ule:
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; AVX: vpminuw %xmm1, %xmm0, %xmm1
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; AVX: vpcmpeqw %xmm1, %xmm0, %xmm0
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}
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define <4 x i32> @v4i32_icmp_uge(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp uwtable {
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%1 = icmp uge <4 x i32> %a, %b
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%2 = sext <4 x i1> %1 to <4 x i32>
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ret <4 x i32> %2
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; SSE2-LABEL: v4i32_icmp_uge:
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; SSE2: movdqa {{.*}}(%rip), %xmm2
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; SSE2: pxor %xmm2, %xmm0
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; SSE2: pxor %xmm1, %xmm2
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; SSE2: pcmpgtd %xmm0, %xmm2
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; SSE2: pcmpeqd %xmm0, %xmm0
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; SSE2: pxor %xmm2, %xmm0
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; SSE41-LABEL: v4i32_icmp_uge:
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; SSE41: pmaxud %xmm0, %xmm1
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; SSE41: pcmpeqd %xmm1, %xmm0
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; AVX-LABEL: v4i32_icmp_uge:
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; AVX: vpmaxud %xmm1, %xmm0, %xmm1
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; AVX: vpcmpeqd %xmm1, %xmm0, %xmm0
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}
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define <4 x i32> @v4i32_icmp_ule(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp uwtable {
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%1 = icmp ule <4 x i32> %a, %b
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%2 = sext <4 x i1> %1 to <4 x i32>
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ret <4 x i32> %2
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; SSE2-LABEL: v4i32_icmp_ule:
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; SSE2: movdqa {{.*}}(%rip), %xmm2
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; SSE2: pxor %xmm2, %xmm1
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; SSE2: pxor %xmm2, %xmm0
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; SSE2: pcmpgtd %xmm1, %xmm0
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; SSE2: pcmpeqd %xmm1, %xmm1
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; SSE2: pxor %xmm0, %xmm1
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; SSE2: movdqa %xmm1, %xmm0
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; SSE41-LABEL: v4i32_icmp_ule:
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; SSE41: pminud %xmm0, %xmm1
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; SSE41: pcmpeqd %xmm1, %xmm0
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; AVX-LABEL: v4i32_icmp_ule:
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; AVX: pminud %xmm1, %xmm0, %xmm1
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; AVX: pcmpeqd %xmm1, %xmm0, %xmm0
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}
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; At one point we were incorrectly constant-folding a setcc to 0x1 instead of
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; 0xff, leading to a constpool load. The instruction doesn't matter here, but it
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; should set all bits to 1.
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define <16 x i8> @test_setcc_constfold_vi8(<16 x i8> %l, <16 x i8> %r) {
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%test1 = icmp eq <16 x i8> %l, %r
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%mask1 = sext <16 x i1> %test1 to <16 x i8>
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%test2 = icmp ne <16 x i8> %l, %r
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%mask2 = sext <16 x i1> %test2 to <16 x i8>
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%res = or <16 x i8> %mask1, %mask2
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ret <16 x i8> %res
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; SSE2-LABEL: test_setcc_constfold_vi8:
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; SSE2: pcmpeqd %xmm0, %xmm0
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; SSE41-LABEL: test_setcc_constfold_vi8:
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; SSE41: pcmpeqd %xmm0, %xmm0
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; AVX-LABEL: test_setcc_constfold_vi8:
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; AVX: vpcmpeqd %xmm0, %xmm0, %xmm0
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}
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; Make sure sensible results come from doing extension afterwards
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define <16 x i8> @test_setcc_constfold_vi1(<16 x i8> %l, <16 x i8> %r) {
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%test1 = icmp eq <16 x i8> %l, %r
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%test2 = icmp ne <16 x i8> %l, %r
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%res = or <16 x i1> %test1, %test2
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%mask = sext <16 x i1> %res to <16 x i8>
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ret <16 x i8> %mask
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; SSE2-LABEL: test_setcc_constfold_vi1:
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; SSE2: pcmpeqd %xmm0, %xmm0
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; SSE41-LABEL: test_setcc_constfold_vi1:
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; SSE41: pcmpeqd %xmm0, %xmm0
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; AVX-LABEL: test_setcc_constfold_vi1:
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; AVX: vpcmpeqd %xmm0, %xmm0, %xmm0
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}
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; 64-bit case is also particularly important, as the constant "-1" is probably
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; just 32-bits wide.
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define <2 x i64> @test_setcc_constfold_vi64(<2 x i64> %l, <2 x i64> %r) {
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%test1 = icmp eq <2 x i64> %l, %r
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%mask1 = sext <2 x i1> %test1 to <2 x i64>
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%test2 = icmp ne <2 x i64> %l, %r
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%mask2 = sext <2 x i1> %test2 to <2 x i64>
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%res = or <2 x i64> %mask1, %mask2
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ret <2 x i64> %res
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; SSE2-LABEL: test_setcc_constfold_vi64:
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; SSE2: pcmpeqd %xmm0, %xmm0
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; SSE41-LABEL: test_setcc_constfold_vi64:
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; SSE41: pcmpeqd %xmm0, %xmm0
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; AVX-LABEL: test_setcc_constfold_vi64:
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; AVX: vpcmpeqd %xmm0, %xmm0, %xmm0
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}
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