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https://github.com/RPCS3/llvm-mirror.git
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bb32a0735a
Summary: Previously 0 and -1 was matched via tablegen rules. But this could cause problems where a physical register was being used where a virtual register was expected (seen in optimizeSelect and TwoAddressInstructionPass). Instead follow AArch64 and match in DAGToDAGISel. Reviewers: eliben, majnemer Subscribers: llvm-commits, aemerson Differential Revision: https://reviews.llvm.org/D27171 llvm-svn: 288215
108 lines
2.3 KiB
LLVM
108 lines
2.3 KiB
LLVM
; RUN: llc < %s | FileCheck %s
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; Test custom lowering for 32-bit integer multiplication.
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target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
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target triple = "lanai"
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; CHECK-LABEL: f6:
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; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
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; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
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; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
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define i32 @f6(i32 inreg %a) #0 {
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%1 = mul nsw i32 %a, 6
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ret i32 %1
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}
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; CHECK-LABEL: f7:
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; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
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; CHECK: sub %r{{[0-9]+}}, %r6, %rv
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define i32 @f7(i32 inreg %a) #0 {
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%1 = mul nsw i32 %a, 7
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ret i32 %1
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}
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; CHECK-LABEL: f8:
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; CHECK: sh %r6, 0x3, %rv
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define i32 @f8(i32 inreg %a) #0 {
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%1 = shl nsw i32 %a, 3
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ret i32 %1
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}
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; CHECK-LABEL: f9:
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; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
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; CHECK: add %r{{[0-9]+}}, %r6, %rv
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define i32 @f9(i32 inreg %a) #0 {
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%1 = mul nsw i32 %a, 9
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ret i32 %1
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}
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; CHECK-LABEL: f10:
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; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
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; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
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; CHECK: add %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
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define i32 @f10(i32 inreg %a) #0 {
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%1 = mul nsw i32 %a, 10
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ret i32 %1
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}
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; CHECK-LABEL: f1280:
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; CHECK: sh %r6, 0x8, %r{{[0-9]+}}
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; CHECK: sh %r6, 0xa, %r{{[0-9]+}}
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; CHECK: add %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
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define i32 @f1280(i32 inreg %a) #0 {
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%1 = mul nsw i32 %a, 1280
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ret i32 %1
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}
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; CHECK-LABEL: fm6:
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; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
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; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
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; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
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define i32 @fm6(i32 inreg %a) #0 {
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%1 = mul nsw i32 %a, -6
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ret i32 %1
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}
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; CHECK-LABEL: fm7:
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; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
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; CHECK: sub %r6, %r{{[0-9]+}}, %rv
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define i32 @fm7(i32 inreg %a) #0 {
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%1 = mul nsw i32 %a, -7
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ret i32 %1
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}
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; CHECK-LABEL: fm8:
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; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
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; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
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define i32 @fm8(i32 inreg %a) #0 {
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%1 = mul nsw i32 %a, -8
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ret i32 %1
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}
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; CHECK-LABEL: fm9:
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; CHECK: sub %r0, %r6, %r{{[0-9]+}}
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; CHECK: sh %r6, 0x3, %r9
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; CHECK: sub %r{{[0-9]+}}, %r9, %rv
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define i32 @fm9(i32 inreg %a) #0 {
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%1 = mul nsw i32 %a, -9
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ret i32 %1
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}
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; CHECK-LABEL: fm10:
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; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
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; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}
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; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
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; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
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define i32 @fm10(i32 inreg %a) #0 {
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%1 = mul nsw i32 %a, -10
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ret i32 %1
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}
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; CHECK-LABEL: h1:
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; CHECK: __mulsi3
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define i32 @h1(i32 inreg %a) #0 {
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%1 = mul i32 %a, -1431655765
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ret i32 %1
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}
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