mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-24 05:23:45 +02:00
43f9c539ae
Previously, instructions without a primary patterns wouldn't get their properties inferred. Now, we use all single-instruction patterns for inference, including 'def : Pat<>' instances. This causes a lot of instruction flags to change. - Many instructions no longer have the UnmodeledSideEffects flag because their flags are now inferred from a pattern. - Instructions with intrinsics will get a mayStore flag if they already have UnmodeledSideEffects and a mayLoad flag if they already have mayStore. This is because intrinsics properties are linear. - Instructions with atomic_load patterns get a mayStore flag because atomic loads can't be reordered. The correct workaround is to create pseudo-instructions instead of using normal loads. PR13693. llvm-svn: 162614
26 lines
694 B
LLVM
26 lines
694 B
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
|
|
; XFAIL: *
|
|
; This is xfailed into we have atomic load pseudos. PR13693.
|
|
|
|
; Check that we generate new value store packet in V4
|
|
|
|
@i = global i32 0, align 4
|
|
@j = global i32 10, align 4
|
|
@k = global i32 100, align 4
|
|
|
|
define i32 @main() nounwind {
|
|
entry:
|
|
; CHECK: memw(r{{[0-9]+}} + #{{[0-9]+}}) = r{{[0-9]+}}.new
|
|
%number1 = alloca i32, align 4
|
|
%number2 = alloca i32, align 4
|
|
%number3 = alloca i32, align 4
|
|
%0 = load i32 * @i, align 4
|
|
store i32 %0, i32* %number1, align 4
|
|
%1 = load i32 * @j, align 4
|
|
store i32 %1, i32* %number2, align 4
|
|
%2 = load i32 * @k, align 4
|
|
store i32 %2, i32* %number3, align 4
|
|
ret i32 %0
|
|
}
|
|
|