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https://github.com/RPCS3/llvm-mirror.git
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283 lines
9.8 KiB
LLVM
283 lines
9.8 KiB
LLVM
; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=corei7 -mattr=-sse4.1 < %s | FileCheck %s
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; Verify that we don't emit packed vector shifts instructions if the
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; condition used by the vector select is a vector of constants.
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define <4 x float> @test1(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test1:
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; CHECK: # BB#0:
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm1
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: orps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <4 x float> @test2(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test2:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsd %xmm0, %xmm1
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <4 x float> @test3(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test3:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsd %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <4 x float> @test4(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test4:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <4 x i1> <i1 false, i1 false, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <4 x float> @test5(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test5:
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; CHECK: # BB#0:
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; CHECK-NEXT: retq
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%1 = select <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test6:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps {{.*#+}} xmm1 = [0,65535,0,65535,0,65535,0,65535]
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; CHECK-NEXT: andps %xmm0, %xmm1
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: orps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>, <8 x i16> %a, <8 x i16> %a
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ret <8 x i16> %1
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}
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define <8 x i16> @test7(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test7:
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; CHECK: # BB#0:
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm1
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: orps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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define <8 x i16> @test8(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test8:
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; CHECK: # BB#0:
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm1
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: orps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test9:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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define <8 x i16> @test10(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test10:
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; CHECK: # BB#0:
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; CHECK-NEXT: retq
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%1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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define <8 x i16> @test11(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test11:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps {{.*#+}} xmm2 = <0,65535,65535,0,u,65535,65535,u>
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; CHECK-NEXT: andps %xmm2, %xmm0
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; CHECK-NEXT: andnps %xmm1, %xmm2
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; CHECK-NEXT: orps %xmm2, %xmm0
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; CHECK-NEXT: retq
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%1 = select <8 x i1> <i1 false, i1 true, i1 true, i1 false, i1 undef, i1 true, i1 true, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test12:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <8 x i1> <i1 false, i1 false, i1 undef, i1 false, i1 false, i1 false, i1 false, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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define <8 x i16> @test13(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test13:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <8 x i1> <i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; Fold (vselect (build_vector AllOnes), N1, N2) -> N1
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define <4 x float> @test14(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test14:
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; CHECK: # BB#0:
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; CHECK-NEXT: retq
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%1 = select <4 x i1> <i1 true, i1 undef, i1 true, i1 undef>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test15:
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; CHECK: # BB#0:
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; CHECK-NEXT: retq
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%1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 undef, i1 undef, i1 true, i1 true, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; Fold (vselect (build_vector AllZeros), N1, N2) -> N2
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define <4 x float> @test16(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test16:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <4 x i1> <i1 false, i1 undef, i1 false, i1 undef>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <8 x i16> @test17(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test17:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 undef, i1 undef, i1 false, i1 false, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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define <4 x float> @test18(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test18:
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; CHECK: # BB#0:
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; CHECK-NEXT: movss %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test19:
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; CHECK: # BB#0:
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; CHECK-NEXT: movss %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %1
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}
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define <2 x double> @test20(<2 x double> %a, <2 x double> %b) {
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; CHECK-LABEL: test20:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsd %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <2 x i1> <i1 false, i1 true>, <2 x double> %a, <2 x double> %b
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ret <2 x double> %1
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}
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define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test21:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsd %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <2 x i1> <i1 false, i1 true>, <2 x i64> %a, <2 x i64> %b
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ret <2 x i64> %1
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}
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define <4 x float> @test22(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test22:
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; CHECK: # BB#0:
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; CHECK-NEXT: movss %xmm0, %xmm1
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <4 x i32> @test23(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test23:
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; CHECK: # BB#0:
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; CHECK-NEXT: movss %xmm0, %xmm1
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %1
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}
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define <2 x double> @test24(<2 x double> %a, <2 x double> %b) {
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; CHECK-LABEL: test24:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsd %xmm0, %xmm1
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <2 x i1> <i1 true, i1 false>, <2 x double> %a, <2 x double> %b
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ret <2 x double> %1
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}
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define <2 x i64> @test25(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test25:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsd %xmm0, %xmm1
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <2 x i1> <i1 true, i1 false>, <2 x i64> %a, <2 x i64> %b
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ret <2 x i64> %1
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}
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define <4 x float> @select_of_shuffles_0(<2 x float> %a0, <2 x float> %b0, <2 x float> %a1, <2 x float> %b1) {
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; CHECK-LABEL: select_of_shuffles_0:
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; CHECK: # BB#0:
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; CHECK-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
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; CHECK-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm3[0]
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; CHECK-NEXT: subps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = shufflevector <2 x float> %a0, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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%2 = shufflevector <2 x float> %a1, <2 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
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%3 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %2, <4 x float> %1
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%4 = shufflevector <2 x float> %b0, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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%5 = shufflevector <2 x float> %b1, <2 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
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%6 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %5, <4 x float> %4
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%7 = fsub <4 x float> %3, %6
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ret <4 x float> %7
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}
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; PR20677
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define <16 x double> @select_illegal(<16 x double> %a, <16 x double> %b) {
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; CHECK-LABEL: select_illegal:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps {{[0-9]+}}(%rsp), %xmm4
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; CHECK-NEXT: movaps {{[0-9]+}}(%rsp), %xmm5
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; CHECK-NEXT: movaps {{[0-9]+}}(%rsp), %xmm6
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; CHECK-NEXT: movaps {{[0-9]+}}(%rsp), %xmm7
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; CHECK-NEXT: movaps %xmm7, 112(%rdi)
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; CHECK-NEXT: movaps %xmm6, 96(%rdi)
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; CHECK-NEXT: movaps %xmm5, 80(%rdi)
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; CHECK-NEXT: movaps %xmm4, 64(%rdi)
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; CHECK-NEXT: movaps %xmm3, 48(%rdi)
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; CHECK-NEXT: movaps %xmm2, 32(%rdi)
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; CHECK-NEXT: movaps %xmm1, 16(%rdi)
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; CHECK-NEXT: movaps %xmm0, (%rdi)
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; CHECK-NEXT: retq
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%sel = select <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x double> %a, <16 x double> %b
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ret <16 x double> %sel
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}
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