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1704a62e0b
This covers both hard and soft float. Hard float is easy, since it's just Legal. Soft float is more involved, because there are several different ways to handle it based on the predicate: one and ueq need not only one, but two libcalls to get a result. Furthermore, we have large differences between the values returned by the AEABI and GNU functions. AEABI functions return a nice 1 or 0 representing true and respectively false. GNU functions generally return a value that needs to be compared against 0 (e.g. for ogt, the value returned by the libcall is > 0 for true). We could introduce redundant comparisons for AEABI as well, but they don't seem easy to remove afterwards, so we do different processing based on whether or not the result really needs to be compared against something (and just truncate if it doesn't). llvm-svn: 307243
299 lines
11 KiB
C++
299 lines
11 KiB
C++
//===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the Machinelegalizer class for ARM.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "ARMLegalizerInfo.h"
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#include "ARMCallLowering.h"
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#include "ARMSubtarget.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
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#include "llvm/CodeGen/LowLevelType.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Target/TargetOpcodes.h"
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using namespace llvm;
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#ifndef LLVM_BUILD_GLOBAL_ISEL
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#error "You shouldn't build this"
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#endif
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static bool AEABI(const ARMSubtarget &ST) {
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return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI();
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}
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ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
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using namespace TargetOpcode;
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const LLT p0 = LLT::pointer(0, 32);
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const LLT s1 = LLT::scalar(1);
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const LLT s8 = LLT::scalar(8);
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const LLT s16 = LLT::scalar(16);
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const LLT s32 = LLT::scalar(32);
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const LLT s64 = LLT::scalar(64);
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setAction({G_FRAME_INDEX, p0}, Legal);
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for (unsigned Op : {G_LOAD, G_STORE}) {
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for (auto Ty : {s1, s8, s16, s32, p0})
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setAction({Op, Ty}, Legal);
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setAction({Op, 1, p0}, Legal);
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}
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for (unsigned Op : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) {
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for (auto Ty : {s1, s8, s16})
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setAction({Op, Ty}, WidenScalar);
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setAction({Op, s32}, Legal);
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}
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for (unsigned Op : {G_SDIV, G_UDIV}) {
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for (auto Ty : {s8, s16})
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setAction({Op, Ty}, WidenScalar);
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if (ST.hasDivideInARMMode())
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setAction({Op, s32}, Legal);
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else
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setAction({Op, s32}, Libcall);
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}
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// FIXME: Support s8 and s16 as well
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for (unsigned Op : {G_SREM, G_UREM})
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if (ST.hasDivideInARMMode())
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setAction({Op, s32}, Lower);
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else if (AEABI(ST))
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setAction({Op, s32}, Custom);
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else
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setAction({Op, s32}, Libcall);
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for (unsigned Op : {G_SEXT, G_ZEXT}) {
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setAction({Op, s32}, Legal);
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for (auto Ty : {s1, s8, s16})
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setAction({Op, 1, Ty}, Legal);
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}
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setAction({G_GEP, p0}, Legal);
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setAction({G_GEP, 1, s32}, Legal);
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setAction({G_SELECT, s32}, Legal);
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setAction({G_SELECT, p0}, Legal);
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setAction({G_SELECT, 1, s1}, Legal);
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setAction({G_CONSTANT, s32}, Legal);
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for (auto Ty : {s1, s8, s16})
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setAction({G_CONSTANT, Ty}, WidenScalar);
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setAction({G_ICMP, s1}, Legal);
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for (auto Ty : {s8, s16})
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setAction({G_ICMP, 1, Ty}, WidenScalar);
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for (auto Ty : {s32, p0})
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setAction({G_ICMP, 1, Ty}, Legal);
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if (!ST.useSoftFloat() && ST.hasVFP2()) {
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setAction({G_FADD, s32}, Legal);
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setAction({G_FADD, s64}, Legal);
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setAction({G_LOAD, s64}, Legal);
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setAction({G_STORE, s64}, Legal);
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setAction({G_FCMP, s1}, Legal);
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setAction({G_FCMP, 1, s32}, Legal);
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} else {
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for (auto Ty : {s32, s64})
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setAction({G_FADD, Ty}, Libcall);
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setAction({G_FCMP, s1}, Legal);
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setAction({G_FCMP, 1, s32}, Custom);
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if (AEABI(ST))
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setFCmpLibcallsAEABI();
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else
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setFCmpLibcallsGNU();
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}
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for (unsigned Op : {G_FREM, G_FPOW})
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for (auto Ty : {s32, s64})
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setAction({Op, Ty}, Libcall);
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computeTables();
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}
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void ARMLegalizerInfo::setFCmpLibcallsAEABI() {
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// FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
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// default-initialized.
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FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
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FCmp32Libcalls[CmpInst::FCMP_OEQ] = {
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{RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp32Libcalls[CmpInst::FCMP_OGE] = {
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{RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp32Libcalls[CmpInst::FCMP_OGT] = {
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{RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp32Libcalls[CmpInst::FCMP_OLE] = {
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{RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp32Libcalls[CmpInst::FCMP_OLT] = {
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{RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_UNO] = {
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{RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp32Libcalls[CmpInst::FCMP_ONE] = {
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{RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE},
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{RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
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FCmp32Libcalls[CmpInst::FCMP_UEQ] = {
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{RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE},
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{RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
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}
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void ARMLegalizerInfo::setFCmpLibcallsGNU() {
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// FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
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// default-initialized.
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FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
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FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}};
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FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}};
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FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}};
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FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
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FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
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FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}};
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FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}};
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FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}};
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FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}};
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FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}};
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FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}};
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FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT},
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{RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
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FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ},
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{RTLIB::UO_F32, CmpInst::ICMP_NE}};
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}
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ARMLegalizerInfo::FCmpLibcallsList
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ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate) const {
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assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate");
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return FCmp32Libcalls[Predicate];
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}
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bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const {
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using namespace TargetOpcode;
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MIRBuilder.setInstr(MI);
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switch (MI.getOpcode()) {
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default:
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return false;
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case G_SREM:
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case G_UREM: {
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unsigned OriginalResult = MI.getOperand(0).getReg();
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auto Size = MRI.getType(OriginalResult).getSizeInBits();
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if (Size != 32)
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return false;
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auto Libcall =
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MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
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// Our divmod libcalls return a struct containing the quotient and the
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// remainder. We need to create a virtual register for it.
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auto &Ctx = MIRBuilder.getMF().getFunction()->getContext();
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Type *ArgTy = Type::getInt32Ty(Ctx);
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StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true);
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auto RetVal = MRI.createGenericVirtualRegister(
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getLLTForType(*RetTy, MIRBuilder.getMF().getDataLayout()));
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auto Status = createLibcall(MIRBuilder, Libcall, {RetVal, RetTy},
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{{MI.getOperand(1).getReg(), ArgTy},
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{MI.getOperand(2).getReg(), ArgTy}});
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if (Status != LegalizerHelper::Legalized)
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return false;
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// The remainder is the second result of divmod. Split the return value into
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// a new, unused register for the quotient and the destination of the
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// original instruction for the remainder.
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MIRBuilder.buildUnmerge(
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{MRI.createGenericVirtualRegister(LLT::scalar(32)), OriginalResult},
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RetVal);
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break;
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}
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case G_FCMP: {
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assert(MRI.getType(MI.getOperand(2).getReg()).getSizeInBits() == 32 &&
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"Unsupported size for FCMP");
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assert(MRI.getType(MI.getOperand(3).getReg()).getSizeInBits() == 32 &&
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"Unsupported size for FCMP");
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auto OriginalResult = MI.getOperand(0).getReg();
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auto Predicate =
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static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
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auto Libcalls = getFCmpLibcalls(Predicate);
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if (Libcalls.empty()) {
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assert((Predicate == CmpInst::FCMP_TRUE ||
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Predicate == CmpInst::FCMP_FALSE) &&
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"Predicate needs libcalls, but none specified");
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MIRBuilder.buildConstant(OriginalResult,
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Predicate == CmpInst::FCMP_TRUE ? 1 : 0);
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return true;
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}
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auto &Ctx = MIRBuilder.getMF().getFunction()->getContext();
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auto *ArgTy = Type::getFloatTy(Ctx);
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auto *RetTy = Type::getInt32Ty(Ctx);
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SmallVector<unsigned, 2> Results;
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for (auto Libcall : Libcalls) {
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auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32));
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auto Status =
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createLibcall(MIRBuilder, Libcall.LibcallID, {LibcallResult, RetTy},
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{{MI.getOperand(2).getReg(), ArgTy},
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{MI.getOperand(3).getReg(), ArgTy}});
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if (Status != LegalizerHelper::Legalized)
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return false;
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auto ProcessedResult =
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Libcalls.size() == 1
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? OriginalResult
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: MRI.createGenericVirtualRegister(MRI.getType(OriginalResult));
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// We have a result, but we need to transform it into a proper 1-bit 0 or
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// 1, taking into account the different peculiarities of the values
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// returned by the comparison functions.
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CmpInst::Predicate ResultPred = Libcall.Predicate;
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if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) {
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// We have a nice 0 or 1, and we just need to truncate it back to 1 bit
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// to keep the types consistent.
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MIRBuilder.buildTrunc(ProcessedResult, LibcallResult);
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} else {
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// We need to compare against 0.
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assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate");
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auto Zero = MRI.createGenericVirtualRegister(LLT::scalar(32));
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MIRBuilder.buildConstant(Zero, 0);
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MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero);
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}
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Results.push_back(ProcessedResult);
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}
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if (Results.size() != 1) {
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assert(Results.size() == 2 && "Unexpected number of results");
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MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]);
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}
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break;
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}
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}
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MI.eraseFromParent();
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return true;
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}
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