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a428f4ce70
Update the SXT[BHW]/UXTW instruction aliases and the shifted reg addressing mode handling. PR19455 and rdar://16650642 llvm-svn: 206495
18 lines
613 B
LLVM
18 lines
613 B
LLVM
; RUN: llc -march=arm64 -mtriple=arm64-apple-darwin < %s | FileCheck %s
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; Check that the peephole optimizer knows about sext and zext instructions.
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; CHECK: test1sext
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define i32 @test1sext(i64 %A, i64 %B, i32* %P, i64 *%P2) nounwind {
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%C = add i64 %A, %B
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; CHECK: add x[[SUM:[0-9]+]], x0, x1
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%D = trunc i64 %C to i32
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%E = shl i64 %C, 32
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%F = ashr i64 %E, 32
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; CHECK: sxtw x[[EXT:[0-9]+]], w[[SUM]]
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store volatile i64 %F, i64 *%P2
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; CHECK: str x[[EXT]]
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store volatile i32 %D, i32* %P
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; Reuse low bits of extended register, don't extend live range of SUM.
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; CHECK: str w[[SUM]]
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ret i32 %D
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}
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