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llvm-mirror/test/CodeGen/ARM64/extend.ll
Jim Grosbach a428f4ce70 ARM64: [su]xtw use W regs as inputs, not X regs.
Update the SXT[BHW]/UXTW instruction aliases and the shifted reg addressing
mode handling.

PR19455 and rdar://16650642

llvm-svn: 206495
2014-04-17 20:47:31 +00:00

16 lines
497 B
LLVM

; RUN: llc < %s -mtriple=arm64-apple-ios | FileCheck %s
@array = external global [0 x i32]
define i64 @foo(i32 %i) {
; CHECK: foo
; CHECK: adrp x[[REG:[0-9]+]], _array@GOTPAGE
; CHECK: ldr x[[REG1:[0-9]+]], [x[[REG]], _array@GOTPAGEOFF]
; CHECK: ldrsw x0, [x[[REG1]], w0, sxtw #2]
; CHECK: ret
%idxprom = sext i32 %i to i64
%arrayidx = getelementptr inbounds [0 x i32]* @array, i64 0, i64 %idxprom
%tmp1 = load i32* %arrayidx, align 4
%conv = sext i32 %tmp1 to i64
ret i64 %conv
}