Yaxun Liu 0c1bf45146 CodeGen: Let frame index value type match alloca addr space ... Recently alloca address space has been added to data layout. Due to this change, pointer returned by alloca may have different size as pointer in address space 0. However, currently the value type of frame index is assumed to be of the same size as pointer in address space 0. This patch fixes that. Most targets assume alloca returning pointer in address space 0, which is the default alloca address space. Therefore it is NFC for them. AMDGCN target with amdgiz environment requires this change since it assumes alloca returning pointer to addr space 5 and its size is 32, which is different from the size of pointer in addr space 0 which is 64. Differential Revision: https://reviews.llvm.org/D32021 llvm-svn: 300864		2017-04-20 18:15:34 +00:00
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AArch64	[GlobalISel] Support vector-of-pointers in LLT	2017-04-19 07:23:57 +00:00
AMDGPU	CodeGen: Let frame index value type match alloca addr space	2017-04-20 18:15:34 +00:00
ARM	[DAG] add splat vector support for 'xor' in SimplifyDemandedBits	2017-04-19 21:23:09 +00:00
AVR	[AVR] Remove the 'multibyte' asm test	2017-04-19 12:13:45 +00:00
BPF
Generic
Hexagon	[Hexagon] Generate proper offset in opt-addr-mode	2017-04-19 15:15:51 +00:00
Inputs
Lanai
Mips	[mips][msa] Mask vectors holding shift amounts	2017-04-20 13:26:46 +00:00
MIR
MSP430
NVPTX
PowerPC	[DAG] add splat vector support for 'xor' in SimplifyDemandedBits	2017-04-19 21:23:09 +00:00
SPARC
SystemZ
Thumb
Thumb2
WebAssembly
WinEH
X86	Temporarily revert r299221 to fix nondeterminism in ThinLTO builder.	2017-04-19 23:16:14 +00:00
XCore