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ca0f4dc4f0
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
70 lines
1.9 KiB
LLVM
70 lines
1.9 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=arm64-none-linux-gnu -disable-fp-elim < %s | FileCheck %s
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declare void @use_addr(i8*)
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@addr = global i8* null
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define void @test_bigframe() {
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; CHECK-LABEL: test_bigframe:
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; CHECK: .cfi_startproc
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%var1 = alloca i8, i32 20000000
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%var2 = alloca i8, i32 16
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%var3 = alloca i8, i32 20000000
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; CHECK: sub sp, sp, #4095, lsl #12
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; CHECK: sub sp, sp, #4095, lsl #12
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; CHECK: sub sp, sp, #1575, lsl #12
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; CHECK: sub sp, sp, #2576
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; CHECK: .cfi_def_cfa_offset 40000032
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; CHECK: add [[TMP:x[0-9]+]], sp, #4095, lsl #12
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; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #787, lsl #12
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; CHECK: add {{x[0-9]+}}, [[TMP1]], #3344
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store volatile i8* %var1, i8** @addr
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%var1plus2 = getelementptr i8* %var1, i32 2
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store volatile i8* %var1plus2, i8** @addr
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; CHECK: add [[TMP:x[0-9]+]], sp, #4095, lsl #12
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; CHECK: add [[TMP1:x[0-9]+]], [[TMP]], #787, lsl #12
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; CHECK: add {{x[0-9]+}}, [[TMP1]], #3328
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store volatile i8* %var2, i8** @addr
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%var2plus2 = getelementptr i8* %var2, i32 2
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store volatile i8* %var2plus2, i8** @addr
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store volatile i8* %var3, i8** @addr
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%var3plus2 = getelementptr i8* %var3, i32 2
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store volatile i8* %var3plus2, i8** @addr
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; CHECK: add sp, sp, #4095, lsl #12
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; CHECK: add sp, sp, #4095, lsl #12
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; CHECK: add sp, sp, #1575, lsl #12
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; CHECK: add sp, sp, #2576
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; CHECK: .cfi_endproc
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ret void
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}
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define void @test_mediumframe() {
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; CHECK-LABEL: test_mediumframe:
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%var1 = alloca i8, i32 1000000
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%var2 = alloca i8, i32 16
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%var3 = alloca i8, i32 1000000
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; CHECK: sub sp, sp, #488, lsl #12
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; CHECK-NEXT: sub sp, sp, #1168
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store volatile i8* %var1, i8** @addr
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; CHECK: add [[VAR1ADDR:x[0-9]+]], sp, #244, lsl #12
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; CHECK: add [[VAR1ADDR]], [[VAR1ADDR]], #592
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; CHECK: add [[VAR2ADDR:x[0-9]+]], sp, #244, lsl #12
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; CHECK: add [[VAR2ADDR]], [[VAR2ADDR]], #576
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store volatile i8* %var2, i8** @addr
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; CHECK: add sp, sp, #488, lsl #12
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; CHECK: add sp, sp, #1168
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ret void
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}
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