mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-22 12:33:33 +02:00
5c443ee383
The virtual registers are serialized using a YAML sequence of YAML inline mappings. Each mapping has the id of the virtual register and the register class. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10981 llvm-svn: 241868
27 lines
562 B
YAML
27 lines
562 B
YAML
# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s
|
|
# This test ensures that the MIR parser reports an error when it encounters an
|
|
# unknown register class.
|
|
|
|
--- |
|
|
|
|
define i32 @test(i32 %a) {
|
|
entry:
|
|
ret i32 %a
|
|
}
|
|
|
|
...
|
|
---
|
|
name: test
|
|
isSSA: true
|
|
tracksRegLiveness: true
|
|
registers:
|
|
# CHECK: [[@LINE+1]]:20: use of undefined register class 'gr3200'
|
|
- {id: 0, class: 'gr3200'}
|
|
body:
|
|
- id: 0
|
|
name: entry
|
|
instructions:
|
|
- 'RETQ %eax'
|
|
...
|
|
|