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055a23f745
Leverage ARM ELF build attribute section to create ELF attribute section for RISC-V. Extract the common part of parsing logic for this section into ELFAttributeParser.[cpp|h] and ELFAttributes.[cpp|h]. Differential Revision: https://reviews.llvm.org/D74023
45 lines
1.2 KiB
C++
45 lines
1.2 KiB
C++
//===-- RISCVAttributes.h - RISCV Attributes --------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains enumerations for RISCV attributes as defined in RISC-V
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// ELF psABI specification.
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//
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// RISC-V ELF psABI specification
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//
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// https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_SUPPORT_RISCVATTRIBUTES_H
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#define LLVM_SUPPORT_RISCVATTRIBUTES_H
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#include "llvm/Support/ELFAttributes.h"
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namespace llvm {
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namespace RISCVAttrs {
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extern const TagNameMap RISCVAttributeTags;
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enum AttrType : unsigned {
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// Attribute types in ELF/.riscv.attributes.
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STACK_ALIGN = 4,
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ARCH = 5,
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UNALIGNED_ACCESS = 6,
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PRIV_SPEC = 8,
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PRIV_SPEC_MINOR = 10,
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PRIV_SPEC_REVISION = 12,
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};
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enum StackAlign { ALIGN_4 = 4, ALIGN_16 = 16 };
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enum { NOT_ALLOWED = 0, ALLOWED = 1 };
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} // namespace RISCVAttrs
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} // namespace llvm
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#endif
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