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113 lines
4.1 KiB
C++
113 lines
4.1 KiB
C++
//===- SparcV9RegisterInfo.h - SparcV9 Register Information Impl -*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SparcV9 implementation of the MRegisterInfo class.
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// It also contains stuff needed to instantiate that class, which would
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// ordinarily be provided by TableGen.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SPARCV9REGISTERINFO_H
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#define SPARCV9REGISTERINFO_H
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#include "llvm/Target/MRegisterInfo.h"
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namespace llvm {
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struct SparcV9RegisterInfo : public MRegisterInfo {
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SparcV9RegisterInfo ();
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const unsigned *getCalleeSaveRegs() const;
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const TargetRegisterClass* const *getCalleeSaveRegClasses() const {
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return 0;
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}
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// The rest of these are stubs... for now.
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, int FrameIndex,
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const TargetRegisterClass *RC) const;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC) const;
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void copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const;
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void eliminateFrameIndex (MachineBasicBlock::iterator MI) const;
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void emitPrologue (MachineFunction &MF) const;
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void emitEpilogue (MachineFunction &MF, MachineBasicBlock &MBB) const;
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};
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} // End llvm namespace
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//===----------------------------------------------------------------------===//
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//
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// The second section of this file (immediately following) contains
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// a *handwritten* SparcV9 unified register number enumeration, which
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// provides a flat namespace containing all the SparcV9 unified
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// register numbers.
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//
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// It would ordinarily be contained in the file SparcV9GenRegisterNames.inc
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// if we were using TableGen to generate the register file description
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// automatically.
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//
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//===----------------------------------------------------------------------===//
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namespace llvm {
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namespace SparcV9 {
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enum {
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// FIXME - Register 0 is not a "non-register" like it is on other targets!!
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// SparcV9IntRegClass(IntRegClassID)
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// - unified register numbers 0 ... 31 (32 regs)
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/* 0 */ o0, o1, o2, o3, o4,
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/* 5 */ o5, o7, l0, l1, l2,
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/* 10 */ l3, l4, l5, l6, l7,
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/* 15 */ i0, i1, i2, i3, i4,
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/* 20 */ i5, i6, i7, g0, g1, // i6 is frame ptr, i7 is ret addr, g0 is zero
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/* 25 */ g2, g3, g4, g5, g6,
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/* 30 */ g7, o6, // o6 is stack ptr
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// SparcV9FloatRegClass(FloatRegClassID)
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// - regs 32 .. 63 are FPSingleRegType, 64 .. 95 are FPDoubleRegType
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// - unified register numbers 32 ... 95 (64 regs)
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/* 32 */ f0, f1, f2,
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/* 35 */ f3, f4, f5, f6, f7,
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/* 40 */ f8, f9, f10, f11, f12,
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/* 45 */ f13, f14, f15, f16, f17,
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/* 50 */ f18, f19, f20, f21, f22,
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/* 55 */ f23, f24, f25, f26, f27,
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/* 60 */ f28, f29, f30, f31, f32,
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/* 65 */ f33, f34, f35, f36, f37,
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/* 70 */ f38, f39, f40, f41, f42,
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/* 75 */ f43, f44, f45, f46, f47,
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/* 80 */ f48, f49, f50, f51, f52,
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/* 85 */ f53, f54, f55, f56, f57,
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/* 90 */ f58, f59, f60, f61, f62,
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/* 95 */ f63,
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// SparcV9IntCCRegClass(IntCCRegClassID)
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// - unified register numbers 96 ... 98 (3 regs)
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/* 96 */ xcc, icc, ccr,
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// SparcV9FloatCCRegClass(FloatCCRegClassID)
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// - unified register numbers 99 ... 102 (4 regs)
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/* 99 */ fcc0, fcc1, fcc2, fcc3,
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// SparcV9SpecialRegClass(SpecialRegClassID)
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// - unified register number 103 (1 reg)
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/* 103 */ fsr
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};
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} // end namespace SparcV9
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} // end namespace llvm
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#endif // SPARCV9REGISTERINFO_H
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