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39f366394d
In order to support hot-patching, we need to make sure the first emitted instruction in a function is a two-byte+ op. This is already the case on x86_64, which seems to always emit two-byte+ ops. However on 32-bit targets this wasn't the case. PATCHABLE_OP now lowers to a XCHG AX, AX, (66 90) like MSVC does. However when targetting pentium3 (/arch:SSE) or i386 (/arch:IA32) targets, we generate MOV EDI,EDI (8B FF) like MSVC does. This is for compatiblity reasons with older tools that rely on this two byte pattern. Differential Revision: https://reviews.llvm.org/D81301
101 lines
3.1 KiB
LLVM
101 lines
3.1 KiB
LLVM
; RUN: llc -mtriple=i386 %s -o - | FileCheck --check-prefixes=CHECK,32 %s
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; RUN: llc -mtriple=x86_64 %s -o - | FileCheck --check-prefixes=CHECK,64 %s
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; RUN: llc -mtriple=x86_64 -function-sections %s -o - | FileCheck --check-prefixes=CHECK,64 %s
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define void @f0() "patchable-function-entry"="0" {
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; CHECK-LABEL: f0:
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; CHECK-NEXT: .Lfunc_begin0:
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; CHECK-NOT: nop
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; CHECK: ret
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; CHECK-NOT: .section __patchable_function_entries
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ret void
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}
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define void @f1() "patchable-function-entry"="1" {
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; CHECK-LABEL: f1:
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; CHECK-NEXT: .Lfunc_begin1:
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; CHECK: nop
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; CHECK-NEXT: ret
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; CHECK: .section __patchable_function_entries,"awo",@progbits,f1{{$}}
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; 32: .p2align 2
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; 32-NEXT: .long .Lfunc_begin1
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; 64: .p2align 3
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; 64-NEXT: .quad .Lfunc_begin1
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ret void
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}
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;; Without -function-sections, f2 is in the same text section as f1.
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;; They share the __patchable_function_entries section.
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;; With -function-sections, f1 and f2 are in different text sections.
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;; Use separate __patchable_function_entries.
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define void @f2() "patchable-function-entry"="2" {
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; CHECK-LABEL: f2:
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; CHECK-NEXT: .Lfunc_begin2:
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; 32: xchgw %ax, %ax
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; 64: xchgw %ax, %ax
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; CHECK-NEXT: ret
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; CHECK: .section __patchable_function_entries,"awo",@progbits,f2{{$}}
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; 32: .p2align 2
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; 32-NEXT: .long .Lfunc_begin2
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; 64: .p2align 3
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; 64-NEXT: .quad .Lfunc_begin2
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ret void
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}
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$f3 = comdat any
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define void @f3() "patchable-function-entry"="3" comdat {
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; CHECK-LABEL: f3:
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; CHECK-NEXT: .Lfunc_begin3:
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; 32: xchgw %ax, %ax
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; 32-NEXT: nop
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; 64: nopl (%rax)
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; CHECK: ret
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; CHECK: .section __patchable_function_entries,"aGwo",@progbits,f3,comdat,f3{{$}}
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; 32: .p2align 2
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; 32-NEXT: .long .Lfunc_begin3
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; 64: .p2align 3
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; 64-NEXT: .quad .Lfunc_begin3
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ret void
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}
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$f5 = comdat any
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define void @f5() "patchable-function-entry"="5" comdat {
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; CHECK-LABEL: f5:
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; CHECK-NEXT: .Lfunc_begin4:
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; 32-COUNT-2: xchgw %ax, %ax
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; 32-NEXT: nop
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; 64: nopl 8(%rax,%rax)
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; CHECK-NEXT: ret
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; CHECK: .section __patchable_function_entries,"aGwo",@progbits,f5,comdat,f5{{$}}
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; 32: .p2align 2
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; 32-NEXT: .long .Lfunc_begin4
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; 64: .p2align 3
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; 64-NEXT: .quad .Lfunc_begin4
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ret void
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}
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;; -fpatchable-function-entry=3,2
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;; "patchable-function-prefix" emits data before the function entry label.
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;; We emit 1-byte NOPs before the function entry, so that with a partial patch,
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;; the remaining instructions do not need to be modified.
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define void @f3_2() "patchable-function-entry"="1" "patchable-function-prefix"="2" {
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; CHECK-LABEL: .type f3_2,@function
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; CHECK-NEXT: .Ltmp0: # @f3_2
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; CHECK-NEXT: nop
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; CHECK-NEXT: nop
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; CHECK-NEXT: f3_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nop
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; CHECK-NEXT: ret
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;; .size does not include the prefix.
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; CHECK: .Lfunc_end5:
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; CHECK-NEXT: .size f3_2, .Lfunc_end5-f3_2
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; CHECK: .section __patchable_function_entries,"awo",@progbits,f3_2{{$}}
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; 32: .p2align 2
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; 32-NEXT: .long .Ltmp0
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; 64: .p2align 3
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; 64-NEXT: .quad .Ltmp0
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%frame = alloca i8, i32 16
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ret void
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}
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