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llvm-mirror/test/CodeGen/Thumb/barrier.ll
Tim Northover 02c638e450 ARM: Use "dmb sy" for barriers on M-class CPUs
The usual default of "dmb ish" (inner-shareable) isn't even a valid instruction
on v6M or v7M (well, it does the same thing but software is strongly
discouraged from using it) so we should emit a full-system barrier there.

llvm-svn: 189483
2013-08-28 14:39:19 +00:00

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LLVM

; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s -check-prefix=V6
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=-db | FileCheck %s -check-prefix=V6
; RUN: llc < %s -march=thumb -mcpu=cortex-m0 | FileCheck %s -check-prefix=V6M
define void @t1() {
; V6-LABEL: t1:
; V6: blx {{_*}}sync_synchronize
; V6M-LABEL: t1:
; V6M: dmb sy
fence seq_cst
ret void
}