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386be85491
Only implemented for R600 so far. SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.
At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.
v2:
- Add support for i8 zext load from stack.
- Coding style fixes
v3:
- Don't reserve registers for indirect addressing when it isn't
being used.
- Fix bug caused by LLVM limiting the number of SubRegIndex
declarations.
v4:
- Fix 64-bit defines
llvm-svn: 174525
76 lines
2.5 KiB
C++
76 lines
2.5 KiB
C++
//===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Parent TargetRegisterInfo class common to all hw codegen targets.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPURegisterInfo.h"
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#include "AMDGPUTargetMachine.h"
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using namespace llvm;
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AMDGPURegisterInfo::AMDGPURegisterInfo(TargetMachine &tm,
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const TargetInstrInfo &tii)
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: AMDGPUGenRegisterInfo(0),
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TM(tm),
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TII(tii)
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{ }
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//===----------------------------------------------------------------------===//
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// Function handling callbacks - Functions are a seldom used feature of GPUS, so
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// they are not supported at this time.
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//===----------------------------------------------------------------------===//
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const uint16_t AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;
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const uint16_t* AMDGPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
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const {
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return &CalleeSavedReg;
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}
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void AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS) const {
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assert(!"Subroutines not supported yet");
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}
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unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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assert(!"Subroutines not supported yet");
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return 0;
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}
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unsigned AMDGPURegisterInfo::getIndirectSubReg(unsigned IndirectIndex) const {
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switch(IndirectIndex) {
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case 0: return AMDGPU::indirect_0;
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case 1: return AMDGPU::indirect_1;
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case 2: return AMDGPU::indirect_2;
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case 3: return AMDGPU::indirect_3;
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case 4: return AMDGPU::indirect_4;
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case 5: return AMDGPU::indirect_5;
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case 6: return AMDGPU::indirect_6;
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case 7: return AMDGPU::indirect_7;
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case 8: return AMDGPU::indirect_8;
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case 9: return AMDGPU::indirect_9;
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case 10: return AMDGPU::indirect_10;
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case 11: return AMDGPU::indirect_11;
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case 12: return AMDGPU::indirect_12;
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case 13: return AMDGPU::indirect_13;
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case 14: return AMDGPU::indirect_14;
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case 15: return AMDGPU::indirect_15;
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default: llvm_unreachable("indirect index out of range");
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}
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}
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#define GET_REGINFO_TARGET_DESC
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#include "AMDGPUGenRegisterInfo.inc"
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