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386be85491
Only implemented for R600 so far. SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.
At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.
v2:
- Add support for i8 zext load from stack.
- Coding style fixes
v3:
- Don't reserve registers for indirect addressing when it isn't
being used.
- Fix bug caused by LLVM limiting the number of SubRegIndex
declarations.
v4:
- Fix 64-bit defines
llvm-svn: 174525
148 lines
5.5 KiB
TableGen
148 lines
5.5 KiB
TableGen
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class R600Reg <string name, bits<16> encoding> : Register<name> {
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let Namespace = "AMDGPU";
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let HWEncoding = encoding;
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}
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class R600RegWithChan <string name, bits<9> sel, string chan> :
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Register <name> {
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field bits<2> chan_encoding = !if(!eq(chan, "X"), 0,
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!if(!eq(chan, "Y"), 1,
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!if(!eq(chan, "Z"), 2,
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!if(!eq(chan, "W"), 3, 0))));
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let HWEncoding{8-0} = sel;
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let HWEncoding{10-9} = chan_encoding;
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let Namespace = "AMDGPU";
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}
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class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> :
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RegisterWithSubRegs<n, subregs> {
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let Namespace = "AMDGPU";
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let SubRegIndices = [sel_x, sel_y, sel_z, sel_w];
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let HWEncoding = encoding;
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}
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foreach Index = 0-127 in {
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foreach Chan = [ "X", "Y", "Z", "W" ] in {
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// 32-bit Temporary Registers
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def T#Index#_#Chan : R600RegWithChan <"T"#Index#"."#Chan, Index, Chan>;
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// Indirect addressing offset registers
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def Addr#Index#_#Chan : R600RegWithChan <"T("#Index#" + AR.x)."#Chan,
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Index, Chan>;
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def TRegMem#Index#_#Chan : R600RegWithChan <"T"#Index#"."#Chan, Index,
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Chan>;
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}
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// 128-bit Temporary Registers
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def T#Index#_XYZW : R600Reg_128 <"T"#Index#".XYZW",
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[!cast<Register>("T"#Index#"_X"),
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!cast<Register>("T"#Index#"_Y"),
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!cast<Register>("T"#Index#"_Z"),
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!cast<Register>("T"#Index#"_W")],
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Index>;
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}
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// Array Base Register holding input in FS
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foreach Index = 448-464 in {
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def ArrayBase#Index : R600Reg<"ARRAY_BASE", Index>;
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}
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// Special Registers
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def ZERO : R600Reg<"0.0", 248>;
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def ONE : R600Reg<"1.0", 249>;
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def NEG_ONE : R600Reg<"-1.0", 249>;
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def ONE_INT : R600Reg<"1", 250>;
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def HALF : R600Reg<"0.5", 252>;
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def NEG_HALF : R600Reg<"-0.5", 252>;
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def ALU_LITERAL_X : R600Reg<"literal.x", 253>;
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def PV_X : R600Reg<"pv.x", 254>;
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def PREDICATE_BIT : R600Reg<"PredicateBit", 0>;
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def PRED_SEL_OFF: R600Reg<"Pred_sel_off", 0>;
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def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 2>;
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def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>;
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def AR_X : R600Reg<"AR.x", 0>;
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def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
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(add (sequence "ArrayBase%u", 448, 464))>;
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// special registers for ALU src operands
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// const buffer reference, SRCx_SEL contains index
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def ALU_CONST : R600Reg<"CBuf", 0>;
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// interpolation param reference, SRCx_SEL contains index
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def ALU_PARAM : R600Reg<"Param", 0>;
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let isAllocatable = 0 in {
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// XXX: Only use the X channel, until we support wider stack widths
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def R600_Addr : RegisterClass <"AMDGPU", [i32], 127, (add (sequence "Addr%u_X", 0, 127))>;
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} // End isAllocatable = 0
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def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32,
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(add (sequence "T%u_X", 0, 127))>;
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def R600_TReg32_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
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(add (sequence "T%u_Y", 0, 127))>;
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def R600_TReg32_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
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(add (sequence "T%u_Z", 0, 127))>;
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def R600_TReg32_W : RegisterClass <"AMDGPU", [f32, i32], 32,
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(add (sequence "T%u_W", 0, 127))>;
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def R600_TReg32 : RegisterClass <"AMDGPU", [f32, i32], 32,
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(interleave R600_TReg32_X, R600_TReg32_Y,
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R600_TReg32_Z, R600_TReg32_W)>;
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def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
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R600_TReg32,
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R600_ArrayBase,
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R600_Addr,
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ZERO, HALF, ONE, ONE_INT, PV_X, ALU_LITERAL_X, NEG_ONE, NEG_HALF,
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ALU_CONST, ALU_PARAM
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)>;
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def R600_Predicate : RegisterClass <"AMDGPU", [i32], 32, (add
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PRED_SEL_OFF, PRED_SEL_ZERO, PRED_SEL_ONE)>;
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def R600_Predicate_Bit: RegisterClass <"AMDGPU", [i32], 32, (add
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PREDICATE_BIT)>;
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def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128,
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(add (sequence "T%u_XYZW", 0, 127))> {
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let CopyCost = -1;
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}
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//===----------------------------------------------------------------------===//
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// Register classes for indirect addressing
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//===----------------------------------------------------------------------===//
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// Super register for all the Indirect Registers. This register class is used
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// by the REG_SEQUENCE instruction to specify the registers to use for direct
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// reads / writes which may be written / read by an indirect address.
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class IndirectSuper<string n, list<Register> subregs> :
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RegisterWithSubRegs<n, subregs> {
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let Namespace = "AMDGPU";
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let SubRegIndices =
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[indirect_0,indirect_1,indirect_2,indirect_3,indirect_4,indirect_5,indirect_6,
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indirect_7,indirect_8,indirect_9,indirect_10,indirect_11,indirect_12,
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indirect_13,indirect_14,indirect_15];
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}
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def IndirectSuperReg : IndirectSuper<"Indirect",
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[TRegMem0_X, TRegMem1_X, TRegMem2_X, TRegMem3_X, TRegMem4_X, TRegMem5_X,
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TRegMem6_X, TRegMem7_X, TRegMem8_X, TRegMem9_X, TRegMem10_X, TRegMem11_X,
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TRegMem12_X, TRegMem13_X, TRegMem14_X, TRegMem15_X]
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>;
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def IndirectReg : RegisterClass<"AMDGPU", [f32, i32], 32, (add IndirectSuperReg)>;
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// This register class defines the registers that are the storage units for
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// the "Indirect Addressing" pseudo memory space.
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// XXX: Only use the X channel, until we support wider stack widths
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def TRegMem : RegisterClass<"AMDGPU", [f32, i32], 32,
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(add (sequence "TRegMem%u_X", 0, 16))
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>;
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