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5570fdd2bb
Reapply r230248. Teach the peephole optimizer to work with MMX instructions by adding entries into the foldable tables. This covers folding opportunities not handled during isel. llvm-svn: 230499
283 lines
8.1 KiB
LLVM
283 lines
8.1 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | FileCheck %s
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define i64 @t0(<1 x i64>* %a, i32* %b) {
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; CHECK-LABEL: t0:
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; CHECK: # BB#0:{{.*}} %entry
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; CHECK: movq (%[[REG1:[a-z]+]]), %mm0
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; CHECK-NEXT: psllq (%[[REG2:[a-z]+]]), %mm0
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; CHECK-NEXT: movd %mm0, %rax
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <1 x i64>* %a to x86_mmx*
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%1 = load x86_mmx* %0, align 8
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%2 = load i32* %b, align 4
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%3 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %1, i32 %2)
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%4 = bitcast x86_mmx %3 to i64
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ret i64 %4
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}
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declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32)
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define i64 @t1(<1 x i64>* %a, i32* %b) {
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; CHECK-LABEL: t1:
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; CHECK: # BB#0:{{.*}} %entry
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; CHECK: movq (%[[REG1]]), %mm0
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; CHECK-NEXT: psrlq (%[[REG2]]), %mm0
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; CHECK-NEXT: movd %mm0, %rax
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <1 x i64>* %a to x86_mmx*
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%1 = load x86_mmx* %0, align 8
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%2 = load i32* %b, align 4
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%3 = tail call x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx %1, i32 %2)
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%4 = bitcast x86_mmx %3 to i64
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ret i64 %4
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}
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declare x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx, i32)
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define i64 @t2(<1 x i64>* %a, i32* %b) {
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; CHECK-LABEL: t2:
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; CHECK: # BB#0:{{.*}} %entry
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; CHECK: movq (%[[REG1]]), %mm0
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; CHECK-NEXT: psllw (%[[REG2]]), %mm0
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; CHECK-NEXT: movd %mm0, %rax
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <1 x i64>* %a to x86_mmx*
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%1 = load x86_mmx* %0, align 8
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%2 = load i32* %b, align 4
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%3 = tail call x86_mmx @llvm.x86.mmx.pslli.w(x86_mmx %1, i32 %2)
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%4 = bitcast x86_mmx %3 to i64
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ret i64 %4
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}
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declare x86_mmx @llvm.x86.mmx.pslli.w(x86_mmx, i32)
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define i64 @t3(<1 x i64>* %a, i32* %b) {
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; CHECK-LABEL: t3:
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; CHECK: # BB#0:{{.*}} %entry
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; CHECK: movq (%[[REG1]]), %mm0
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; CHECK-NEXT: psrlw (%[[REG2]]), %mm0
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; CHECK-NEXT: movd %mm0, %rax
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <1 x i64>* %a to x86_mmx*
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%1 = load x86_mmx* %0, align 8
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%2 = load i32* %b, align 4
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%3 = tail call x86_mmx @llvm.x86.mmx.psrli.w(x86_mmx %1, i32 %2)
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%4 = bitcast x86_mmx %3 to i64
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ret i64 %4
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}
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declare x86_mmx @llvm.x86.mmx.psrli.w(x86_mmx, i32)
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define i64 @t4(<1 x i64>* %a, i32* %b) {
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; CHECK-LABEL: t4:
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; CHECK: # BB#0:{{.*}} %entry
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; CHECK: movq (%[[REG1]]), %mm0
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; CHECK-NEXT: pslld (%[[REG2]]), %mm0
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; CHECK-NEXT: movd %mm0, %rax
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <1 x i64>* %a to x86_mmx*
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%1 = load x86_mmx* %0, align 8
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%2 = load i32* %b, align 4
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%3 = tail call x86_mmx @llvm.x86.mmx.pslli.d(x86_mmx %1, i32 %2)
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%4 = bitcast x86_mmx %3 to i64
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ret i64 %4
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}
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declare x86_mmx @llvm.x86.mmx.pslli.d(x86_mmx, i32)
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define i64 @t5(<1 x i64>* %a, i32* %b) {
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; CHECK-LABEL: t5:
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; CHECK: # BB#0:{{.*}} %entry
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; CHECK: movq (%[[REG1]]), %mm0
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; CHECK-NEXT: psrld (%[[REG2]]), %mm0
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; CHECK-NEXT: movd %mm0, %rax
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <1 x i64>* %a to x86_mmx*
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%1 = load x86_mmx* %0, align 8
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%2 = load i32* %b, align 4
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%3 = tail call x86_mmx @llvm.x86.mmx.psrli.d(x86_mmx %1, i32 %2)
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%4 = bitcast x86_mmx %3 to i64
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ret i64 %4
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}
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declare x86_mmx @llvm.x86.mmx.psrli.d(x86_mmx, i32)
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define i64 @t6(<1 x i64>* %a, i32* %b) {
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; CHECK-LABEL: t6:
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; CHECK: # BB#0:{{.*}} %entry
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; CHECK: movq (%[[REG1]]), %mm0
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; CHECK-NEXT: psraw (%[[REG2]]), %mm0
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; CHECK-NEXT: movd %mm0, %rax
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <1 x i64>* %a to x86_mmx*
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%1 = load x86_mmx* %0, align 8
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%2 = load i32* %b, align 4
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%3 = tail call x86_mmx @llvm.x86.mmx.psrai.w(x86_mmx %1, i32 %2)
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%4 = bitcast x86_mmx %3 to i64
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ret i64 %4
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}
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declare x86_mmx @llvm.x86.mmx.psrai.w(x86_mmx, i32)
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define i64 @t7(<1 x i64>* %a, i32* %b) {
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; CHECK-LABEL: t7:
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; CHECK: # BB#0:{{.*}} %entry
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; CHECK: movq (%[[REG1]]), %mm0
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; CHECK-NEXT: psrad (%[[REG2]]), %mm0
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; CHECK-NEXT: movd %mm0, %rax
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <1 x i64>* %a to x86_mmx*
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%1 = load x86_mmx* %0, align 8
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%2 = load i32* %b, align 4
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%3 = tail call x86_mmx @llvm.x86.mmx.psrai.d(x86_mmx %1, i32 %2)
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%4 = bitcast x86_mmx %3 to i64
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ret i64 %4
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}
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declare x86_mmx @llvm.x86.mmx.psrai.d(x86_mmx, i32)
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define i64 @tt0(x86_mmx %t, x86_mmx* %q) {
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; CHECK-LABEL: tt0:
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; CHECK: # BB#0:{{.*}} %entry
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; CHECK: paddb (%[[REG3:[a-z]+]]), %mm0
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; CHECK-NEXT: movd %mm0, %rax
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; CHECK-NEXT: emms
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; CHECK-NEXT: retq
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entry:
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%v = load x86_mmx* %q
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%u = tail call x86_mmx @llvm.x86.mmx.padd.b(x86_mmx %t, x86_mmx %v)
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%s = bitcast x86_mmx %u to i64
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call void @llvm.x86.mmx.emms()
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ret i64 %s
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}
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declare x86_mmx @llvm.x86.mmx.padd.b(x86_mmx, x86_mmx)
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declare void @llvm.x86.mmx.emms()
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define i64 @tt1(x86_mmx %t, x86_mmx* %q) {
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; CHECK-LABEL: tt1:
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; CHECK: # BB#0:{{.*}} %entry
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; CHECK: paddw (%[[REG3]]), %mm0
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; CHECK-NEXT: movd %mm0, %rax
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; CHECK-NEXT: emms
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; CHECK-NEXT: retq
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entry:
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%v = load x86_mmx* %q
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%u = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %t, x86_mmx %v)
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%s = bitcast x86_mmx %u to i64
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call void @llvm.x86.mmx.emms()
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ret i64 %s
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}
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declare x86_mmx @llvm.x86.mmx.padd.w(x86_mmx, x86_mmx)
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define i64 @tt2(x86_mmx %t, x86_mmx* %q) {
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; CHECK-LABEL: tt2:
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; CHECK: # BB#0:{{.*}} %entry
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; CHECK: paddd (%[[REG3]]), %mm0
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; CHECK-NEXT: movd %mm0, %rax
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; CHECK-NEXT: emms
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; CHECK-NEXT: retq
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entry:
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%v = load x86_mmx* %q
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%u = tail call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %t, x86_mmx %v)
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%s = bitcast x86_mmx %u to i64
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call void @llvm.x86.mmx.emms()
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ret i64 %s
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}
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declare x86_mmx @llvm.x86.mmx.padd.d(x86_mmx, x86_mmx)
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define i64 @tt3(x86_mmx %t, x86_mmx* %q) {
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; CHECK-LABEL: tt3:
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; CHECK: # BB#0:{{.*}} %entry
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; CHECK: paddq (%[[REG3]]), %mm0
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; CHECK-NEXT: movd %mm0, %rax
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; CHECK-NEXT: emms
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; CHECK-NEXT: retq
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entry:
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%v = load x86_mmx* %q
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%u = tail call x86_mmx @llvm.x86.mmx.padd.q(x86_mmx %t, x86_mmx %v)
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%s = bitcast x86_mmx %u to i64
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call void @llvm.x86.mmx.emms()
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ret i64 %s
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}
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declare x86_mmx @llvm.x86.mmx.padd.q(x86_mmx, x86_mmx)
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define i64 @tt4(x86_mmx %t, x86_mmx* %q) {
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; CHECK-LABEL: tt4:
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; CHECK: # BB#0:{{.*}} %entry
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; CHECK: paddusb (%[[REG3]]), %mm0
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; CHECK-NEXT: movd %mm0, %rax
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; CHECK-NEXT: emms
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; CHECK-NEXT: retq
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entry:
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%v = load x86_mmx* %q
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%u = tail call x86_mmx @llvm.x86.mmx.paddus.b(x86_mmx %t, x86_mmx %v)
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%s = bitcast x86_mmx %u to i64
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call void @llvm.x86.mmx.emms()
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ret i64 %s
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}
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declare x86_mmx @llvm.x86.mmx.paddus.b(x86_mmx, x86_mmx)
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define i64 @tt5(x86_mmx %t, x86_mmx* %q) {
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; CHECK-LABEL: tt5:
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; CHECK: # BB#0:{{.*}} %entry
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; CHECK: paddusw (%[[REG3]]), %mm0
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; CHECK-NEXT: movd %mm0, %rax
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; CHECK-NEXT: emms
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; CHECK-NEXT: retq
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entry:
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%v = load x86_mmx* %q
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%u = tail call x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx %t, x86_mmx %v)
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%s = bitcast x86_mmx %u to i64
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call void @llvm.x86.mmx.emms()
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ret i64 %s
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}
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declare x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx, x86_mmx)
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define i64 @tt6(x86_mmx %t, x86_mmx* %q) {
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; CHECK-LABEL: tt6:
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; CHECK: # BB#0:{{.*}} %entry
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; CHECK: psrlw (%[[REG3]]), %mm0
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; CHECK-NEXT: movd %mm0, %rax
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; CHECK-NEXT: emms
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; CHECK-NEXT: retq
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entry:
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%v = load x86_mmx* %q
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%u = tail call x86_mmx @llvm.x86.mmx.psrl.w(x86_mmx %t, x86_mmx %v)
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%s = bitcast x86_mmx %u to i64
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call void @llvm.x86.mmx.emms()
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ret i64 %s
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}
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declare x86_mmx @llvm.x86.mmx.psrl.w(x86_mmx, x86_mmx)
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define i64 @tt7(x86_mmx %t, x86_mmx* %q) {
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; CHECK-LABEL: tt7:
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; CHECK: # BB#0:{{.*}} %entry
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; CHECK: psrld (%[[REG3]]), %mm0
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; CHECK-NEXT: movd %mm0, %rax
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; CHECK-NEXT: emms
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; CHECK-NEXT: retq
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entry:
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%v = load x86_mmx* %q
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%u = tail call x86_mmx @llvm.x86.mmx.psrl.d(x86_mmx %t, x86_mmx %v)
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%s = bitcast x86_mmx %u to i64
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call void @llvm.x86.mmx.emms()
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ret i64 %s
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}
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declare x86_mmx @llvm.x86.mmx.psrl.d(x86_mmx, x86_mmx)
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define i64 @tt8(x86_mmx %t, x86_mmx* %q) {
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; CHECK-LABEL: tt8:
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; CHECK: # BB#0:{{.*}} %entry
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; CHECK: psrlq (%[[REG3]]), %mm0
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; CHECK-NEXT: movd %mm0, %rax
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; CHECK-NEXT: emms
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; CHECK-NEXT: retq
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entry:
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%v = load x86_mmx* %q
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%u = tail call x86_mmx @llvm.x86.mmx.psrl.q(x86_mmx %t, x86_mmx %v)
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%s = bitcast x86_mmx %u to i64
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call void @llvm.x86.mmx.emms()
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ret i64 %s
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}
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declare x86_mmx @llvm.x86.mmx.psrl.q(x86_mmx, x86_mmx)
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