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c29399e54e
using IL, ILA, et. al. v2i64 and i64 are now supported by the select bits (SELB) instruction. - Add missing comparison operations (testcase forthcoming) - More multiclass refactoring. llvm-svn: 47973
197 lines
8.0 KiB
TableGen
197 lines
8.0 KiB
TableGen
//===- SPUNodes.td - Specialized SelectionDAG nodes used for CellSPU ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Type profiles and SelectionDAG nodes used by CellSPU
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//
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//===----------------------------------------------------------------------===//
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// Type profile for a call sequence
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def SDT_SPUCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
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// SPU_GenControl: Type profile for generating control words for insertions
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def SPU_GenControl : SDTypeProfile<1, 1, []>;
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def SPUvecinsmask : SDNode<"SPUISD::INSERT_MASK", SPU_GenControl, []>;
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPUCallSeq,
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[SDNPHasChain, SDNPOutFlag]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPUCallSeq,
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[SDNPHasChain, SDNPOutFlag]>;
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//===----------------------------------------------------------------------===//
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// Operand constraints:
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//===----------------------------------------------------------------------===//
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def SDT_SPUCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
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def SPUcall : SDNode<"SPUISD::CALL", SDT_SPUCall,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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// Operand type constraints for vector shuffle/permute operations
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def SDT_SPUshuffle : SDTypeProfile<1, 3, [
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SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
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]>;
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// Unary, binary v16i8 operator type constraints:
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def SPUv16i8_unop: SDTypeProfile<1, 1, [
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SDTCisVT<0, v16i8>, SDTCisSameAs<0, 1>]>;
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def SPUv16i8_binop: SDTypeProfile<1, 2, [
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SDTCisVT<0, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
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// Binary v8i16 operator type constraints:
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def SPUv8i16_unop: SDTypeProfile<1, 1, [
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SDTCisVT<0, v8i16>, SDTCisSameAs<0, 1>]>;
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def SPUv8i16_binop: SDTypeProfile<1, 2, [
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SDTCisVT<0, v8i16>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
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// Binary v4i32 operator type constraints:
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def SPUv4i32_unop: SDTypeProfile<1, 1, [
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SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>]>;
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def SPUv4i32_binop: SDTypeProfile<1, 2, [
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SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
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// FSMBI type constraints: There are several variations for the various
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// vector types (this avoids having to bit_convert all over the place.)
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def SPUfsmbi_type: SDTypeProfile<1, 1, [
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/* SDTCisVT<1, i32> */ SDTCisInt<1>]>;
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// SELB type constraints:
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def SPUselb_type: SDTypeProfile<1, 3, [
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SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisSameAs<0, 3> ]>;
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// SPU Vector shift pseudo-instruction type constraints
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def SPUvecshift_type: SDTypeProfile<1, 2, [
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SDTCisSameAs<0, 1>, SDTCisInt<2>]>;
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//===----------------------------------------------------------------------===//
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// Synthetic/pseudo-instructions
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//===----------------------------------------------------------------------===//
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// SPU CNTB:
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def SPUcntb_v16i8: SDNode<"SPUISD::CNTB", SPUv16i8_unop, []>;
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def SPUcntb_v8i16: SDNode<"SPUISD::CNTB", SPUv8i16_unop, []>;
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def SPUcntb_v4i32: SDNode<"SPUISD::CNTB", SPUv4i32_unop, []>;
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// SPU vector shuffle node, matched by the SPUISD::SHUFB enum (see
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// SPUISelLowering.h):
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def SPUshuffle: SDNode<"SPUISD::SHUFB", SDT_SPUshuffle, []>;
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// SPU 16-bit multiply
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def SPUmpy_v16i8: SDNode<"SPUISD::MPY", SPUv16i8_binop, []>;
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def SPUmpy_v8i16: SDNode<"SPUISD::MPY", SPUv8i16_binop, []>;
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def SPUmpy_v4i32: SDNode<"SPUISD::MPY", SPUv4i32_binop, []>;
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// SPU multiply unsigned, used in instruction lowering for v4i32
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// multiplies:
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def SPUmpyu_v4i32: SDNode<"SPUISD::MPYU", SPUv4i32_binop, []>;
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def SPUmpyu_i32: SDNode<"SPUISD::MPYU", SDTIntBinOp, []>;
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// SPU 16-bit multiply high x low, shift result 16-bits
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// Used to compute intermediate products for 32-bit multiplies
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def SPUmpyh_v4i32: SDNode<"SPUISD::MPYH", SPUv4i32_binop, []>;
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def SPUmpyh_i32: SDNode<"SPUISD::MPYH", SDTIntBinOp, []>;
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// SPU 16-bit multiply high x high, 32-bit product
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// Used to compute intermediate products for 16-bit multiplies
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def SPUmpyhh_v8i16: SDNode<"SPUISD::MPYHH", SPUv8i16_binop, []>;
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// Shift left quadword by bits and bytes
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def SPUshlquad_l_bits: SDNode<"SPUISD::SHLQUAD_L_BITS", SPUvecshift_type, []>;
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def SPUshlquad_l_bytes: SDNode<"SPUISD::SHLQUAD_L_BYTES", SPUvecshift_type, []>;
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// Vector shifts (ISD::SHL,SRL,SRA are for _integers_ only):
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def SPUvec_shl: SDNode<"SPUISD::VEC_SHL", SPUvecshift_type, []>;
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def SPUvec_srl: SDNode<"SPUISD::VEC_SRL", SPUvecshift_type, []>;
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def SPUvec_sra: SDNode<"SPUISD::VEC_SRA", SPUvecshift_type, []>;
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def SPUvec_rotl: SDNode<"SPUISD::VEC_ROTL", SPUvecshift_type, []>;
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def SPUvec_rotr: SDNode<"SPUISD::VEC_ROTR", SPUvecshift_type, []>;
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def SPUrotquad_rz_bytes: SDNode<"SPUISD::ROTQUAD_RZ_BYTES",
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SPUvecshift_type, []>;
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def SPUrotquad_rz_bits: SDNode<"SPUISD::ROTQUAD_RZ_BITS",
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SPUvecshift_type, []>;
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def SPUrotbytes_right_sfill: SDNode<"SPUISD::ROTBYTES_RIGHT_S",
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SPUvecshift_type, []>;
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def SPUrotbytes_left: SDNode<"SPUISD::ROTBYTES_LEFT",
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SPUvecshift_type, []>;
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def SPUrotbytes_left_chained : SDNode<"SPUISD::ROTBYTES_LEFT_CHAINED",
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SPUvecshift_type, [SDNPHasChain]>;
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// SPU form select mask for bytes, immediate
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def SPUfsmbi: SDNode<"SPUISD::FSMBI", SPUfsmbi_type, []>;
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// SPU select bits instruction
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def SPUselb: SDNode<"SPUISD::SELB", SPUselb_type, []>;
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// SPU floating point interpolate
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def SPUinterpolate : SDNode<"SPUISD::FPInterp", SDTFPBinOp, []>;
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// SPU floating point reciprocal estimate (used for fdiv)
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def SPUreciprocalEst: SDNode<"SPUISD::FPRecipEst", SDTFPUnaryOp, []>;
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def SDTpromote_scalar: SDTypeProfile<1, 1, []>;
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def SPUpromote_scalar: SDNode<"SPUISD::PROMOTE_SCALAR", SDTpromote_scalar, []>;
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def SPU_vec_demote : SDTypeProfile<1, 1, []>;
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def SPUextract_elt0: SDNode<"SPUISD::EXTRACT_ELT0", SPU_vec_demote, []>;
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def SPU_vec_demote_chained : SDTypeProfile<1, 2, []>;
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def SPUextract_elt0_chained: SDNode<"SPUISD::EXTRACT_ELT0_CHAINED",
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SPU_vec_demote_chained, [SDNPHasChain]>;
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def SPUextract_i1_sext: SDNode<"SPUISD::EXTRACT_I1_SEXT", SPU_vec_demote, []>;
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def SPUextract_i1_zext: SDNode<"SPUISD::EXTRACT_I1_ZEXT", SPU_vec_demote, []>;
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def SPUextract_i8_sext: SDNode<"SPUISD::EXTRACT_I8_SEXT", SPU_vec_demote, []>;
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def SPUextract_i8_zext: SDNode<"SPUISD::EXTRACT_I8_ZEXT", SPU_vec_demote, []>;
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// Address high and low components, used for [r+r] type addressing
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def SPUhi : SDNode<"SPUISD::Hi", SDTIntBinOp, []>;
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def SPUlo : SDNode<"SPUISD::Lo", SDTIntBinOp, []>;
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// PC-relative address
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def SPUpcrel : SDNode<"SPUISD::PCRelAddr", SDTIntBinOp, []>;
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// A-Form local store addresses
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def SPUaform : SDNode<"SPUISD::AFormAddr", SDTIntBinOp, []>;
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// Indirect [D-Form "imm($reg)" and X-Form "$reg($reg)"] addresses
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def SPUindirect : SDNode<"SPUISD::IndirectAddr", SDTIntBinOp, []>;
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// SPU 32-bit sign-extension to 64-bits
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def SPUsext32_to_64: SDNode<"SPUISD::SEXT32TO64", SDTIntExtendOp, []>;
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// Branches:
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def SPUbrnz : SDNode<"SPUISD::BR_NOTZERO", SDTBrcond, [SDNPHasChain]>;
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def SPUbrz : SDNode<"SPUISD::BR_ZERO", SDTBrcond, [SDNPHasChain]>;
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/* def SPUbinz : SDNode<"SPUISD::BR_NOTZERO", SDTBrind, [SDNPHasChain]>;
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def SPUbiz : SDNode<"SPUISD::BR_ZERO", SPUBrind, [SDNPHasChain]>; */
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//===----------------------------------------------------------------------===//
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// Constraints: (taken from PPCInstrInfo.td)
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//===----------------------------------------------------------------------===//
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class RegConstraint<string C> {
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string Constraints = C;
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}
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class NoEncode<string E> {
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string DisableEncoding = E;
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}
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//===----------------------------------------------------------------------===//
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// Return (flag isn't quite what it means: the operations are flagged so that
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// instruction scheduling doesn't disassociate them.)
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//===----------------------------------------------------------------------===//
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def retflag : SDNode<"SPUISD::RET_FLAG", SDTNone,
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[SDNPHasChain, SDNPOptInFlag]>;
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