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AArch64 has feature predicates for NEON, FP and CRYPTO instructions. This allows the compiler to generate code without using FP, NEON or CRYPTO instructions. llvm-svn: 206949
21 lines
812 B
ArmAsm
21 lines
812 B
ArmAsm
// RUN: not llvm-mc -triple arm64 -mattr=neon -show-encoding < %s 2>%t | FileCheck %s
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// RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
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ST4 {v0.8B-v3.8B}, [x0]
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ST4 {v0.4H-v3.4H}, [x0]
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// CHECK: st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x00,0x00,0x0c]
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// CHECK: st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x0] // encoding: [0x00,0x04,0x00,0x0c]
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ST4 {v0.8B-v4.8B}, [x0]
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ST4 {v0.8B-v3.8B,v4.8B}, [x0]
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ST4 {v0.8B-v3.8H}, [x0]
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ST4 {v0.8B-v3.16B}, [x0]
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ST4 {v0.8B-},[x0]
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// CHECK-ERRORS: error: invalid number of vectors
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// CHECK-ERRORS: error: unexpected token in argument list
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// CHECK-ERRORS: error: mismatched register size suffix
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// CHECK-ERRORS: error: mismatched register size suffix
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// CHECK-ERRORS: error: vector register expected
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