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Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
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1.1 KiB
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27 lines
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..
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid8_dst_mimg_gather4:
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vdst
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===========================
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Image data to load by an *image_gather4* instruction.
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*Size:* 4 data elements by default. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
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:ref:`d16<amdgpu_synid_d16>` and :ref:`tfe<amdgpu_synid_tfe>` affect operand size as follows:
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* :ref:`d16<amdgpu_synid_d16>` has different meaning for GFX8.0 and GFX8.1:
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* For GFX8.0 this modifier does not affect size of data elements in registers. Data in registers are stored in low 16 bits, high 16 bits are unused. There is no packing.
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* Starting from GFX8.1 this modifier specifies that data elements in registers are packed; each value occupies 16 bits.
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* :ref:`tfe<amdgpu_synid_tfe>` adds one dword if specified.
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*Operands:* :ref:`v<amdgpu_synid_v>`
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