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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-22 20:43:44 +02:00
llvm-mirror/test/CodeGen
2017-09-16 01:43:21 +00:00
..
AArch64 [AArch64] allow v8f16 types when FullFP16 is supported 2017-09-15 09:24:48 +00:00
AMDGPU AMDGPU: Fix violating constant bus restriction 2017-09-14 20:54:29 +00:00
ARC
ARM Add newline to end of test file. NFC. 2017-09-14 14:48:59 +00:00
AVR
BPF
Generic
Hexagon [IfConversion] More simple, correct dead/kill liveness handling 2017-09-14 15:53:11 +00:00
Inputs
Lanai
Mips [mips] Pick the right variant of DINS upfront and enable target instruction verification 2017-09-14 10:58:00 +00:00
MIR
MSP430
Nios2
NVPTX
PowerPC [XRay][CodeGen] Use the current function symbol as the associated symbol for the instrumentation map 2017-09-14 07:08:23 +00:00
SPARC
SystemZ Move llvm/test/CodeGen/X86/clear-liverange-spillreg.mir to SystemZ. It was in wrong place. 2017-09-14 00:03:23 +00:00
Thumb
Thumb2
WebAssembly
WinEH
X86 [X86] Remove slash in front of a CHECK line in a test. 2017-09-16 01:43:21 +00:00
XCore