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134 lines
3.7 KiB
TableGen
134 lines
3.7 KiB
TableGen
//===- HexagonCallingConv.td ----------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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class CCIfArgIsVarArg<CCAction A>
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: CCIf<"State.isVarArg() && "
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"ValNo >= static_cast<HexagonCCState&>(State)"
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".getNumNamedVarArgParams()", A>;
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def CC_HexagonStack: CallingConv<[
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CCIfType<[i32,v2i16,v4i8],
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CCAssignToStack<4,4>>,
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CCIfType<[i64,v2i32,v4i16,v8i8],
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CCAssignToStack<8,8>>
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]>;
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def CC_Hexagon: CallingConv<[
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CCIfType<[i1,i8,i16],
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CCPromoteToType<i32>>,
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CCIfType<[f32],
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CCBitConvertToType<i32>>,
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CCIfType<[f64],
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CCBitConvertToType<i64>>,
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CCIfByVal<
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CCPassByVal<8,8>>,
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CCIfArgIsVarArg<
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CCDelegateTo<CC_HexagonStack>>,
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// Pass split values in pairs, allocate odd register if necessary.
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CCIfType<[i32],
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CCIfSplit<
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CCCustom<"CC_SkipOdd">>>,
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CCIfType<[i32,v2i16,v4i8],
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CCAssignToReg<[R0,R1,R2,R3,R4,R5]>>,
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// Make sure to allocate any skipped 32-bit register, so it does not get
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// allocated to a subsequent 32-bit value.
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CCIfType<[i64,v2i32,v4i16,v8i8],
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CCCustom<"CC_SkipOdd">>,
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CCIfType<[i64,v2i32,v4i16,v8i8],
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CCAssignToReg<[D0,D1,D2]>>,
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CCDelegateTo<CC_HexagonStack>
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]>;
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def RetCC_Hexagon: CallingConv<[
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CCIfType<[i1,i8,i16],
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CCPromoteToType<i32>>,
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CCIfType<[f32],
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CCBitConvertToType<i32>>,
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CCIfType<[f64],
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CCBitConvertToType<i64>>,
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// Small structures are returned in a pair of registers, (which is
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// always r1:0). In such case, what is returned are two i32 values
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// without any additional information (in ArgFlags) stating that
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// they are parts of a structure. Because of that there is no way
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// to differentiate that situation from an attempt to return two
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// values, so always assign R0 and R1.
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CCIfSplit<
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CCAssignToReg<[R0,R1]>>,
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CCIfType<[i32,v2i16,v4i8],
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CCAssignToReg<[R0,R1]>>,
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CCIfType<[i64,v2i32,v4i16,v8i8],
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CCAssignToReg<[D0]>>
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]>;
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class CCIfHvx64<CCAction A>
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: CCIf<"State.getMachineFunction().getSubtarget<HexagonSubtarget>()"
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".useHVX64BOps()", A>;
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class CCIfHvx128<CCAction A>
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: CCIf<"State.getMachineFunction().getSubtarget<HexagonSubtarget>()"
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".useHVX128BOps()", A>;
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def CC_Hexagon_HVX: CallingConv<[
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// HVX 64-byte mode
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CCIfHvx64<
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CCIfType<[v16i32,v32i16,v64i8],
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CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
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CCIfHvx64<
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CCIfType<[v32i32,v64i16,v128i8],
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CCAssignToReg<[W0,W1,W2,W3,W4,W5,W6,W7]>>>,
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CCIfHvx64<
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CCIfType<[v16i32,v32i16,v64i8],
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CCAssignToStack<64,64>>>,
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CCIfHvx64<
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CCIfType<[v32i32,v64i16,v128i8],
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CCAssignToStack<128,64>>>,
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// HVX 128-byte mode
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CCIfHvx128<
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CCIfType<[v32i32,v64i16,v128i8],
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CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
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CCIfHvx128<
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CCIfType<[v64i32,v128i16,v256i8],
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CCAssignToReg<[W0,W1,W2,W3,W4,W5,W6,W7]>>>,
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CCIfHvx128<
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CCIfType<[v32i32,v64i16,v128i8],
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CCAssignToStack<128,128>>>,
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CCIfHvx128<
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CCIfType<[v64i32,v128i16,v256i8],
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CCAssignToStack<256,128>>>,
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CCDelegateTo<CC_Hexagon>
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]>;
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def RetCC_Hexagon_HVX: CallingConv<[
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// HVX 64-byte mode
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CCIfHvx64<
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CCIfType<[v16i32,v32i16,v64i8],
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CCAssignToReg<[V0]>>>,
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CCIfHvx64<
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CCIfType<[v32i32,v64i16,v128i8],
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CCAssignToReg<[W0]>>>,
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// HVX 128-byte mode
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CCIfHvx128<
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CCIfType<[v32i32,v64i16,v128i8],
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CCAssignToReg<[V0]>>>,
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CCIfHvx128<
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CCIfType<[v64i32,v128i16,v256i8],
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CCAssignToReg<[W0]>>>,
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CCDelegateTo<RetCC_Hexagon>
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]>;
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