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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
180 lines
8.7 KiB
TableGen
180 lines
8.7 KiB
TableGen
//===--- HexagonMapAsm2IntrinV62.gen.td -----------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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multiclass T_VR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
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(MI HvxVR:$src1, IntRegs:$src2)>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, IntRegs:$src2),
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(MI HvxVR:$src1, IntRegs:$src2)>;
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}
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multiclass T_VVL_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
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(MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
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IntRegsLow8:$src3),
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(MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
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}
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multiclass T_VV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
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(MI HvxVR:$src1, HvxVR:$src2)>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2),
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(MI HvxVR:$src1, HvxVR:$src2)>;
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}
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multiclass T_WW_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
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(MI HvxWR:$src1, HvxWR:$src2)>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2),
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(MI HvxWR:$src1, HvxWR:$src2)>;
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}
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multiclass T_WVV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
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(MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
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HvxVR:$src3),
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(MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
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}
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multiclass T_WR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
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(MI HvxWR:$src1, IntRegs:$src2)>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, IntRegs:$src2),
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(MI HvxWR:$src1, IntRegs:$src2)>;
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}
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multiclass T_WWR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
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(MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2,
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IntRegs:$src3),
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(MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
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}
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multiclass T_VVR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
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(MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
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IntRegs:$src3),
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(MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
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}
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multiclass T_ZR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID HvxQR:$src1, IntRegs:$src2),
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(MI HvxQR:$src1, IntRegs:$src2)>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2),
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(MI HvxQR:$src1, IntRegs:$src2)>;
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}
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multiclass T_VZR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),
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(MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxQR:$src2,
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IntRegs:$src3),
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(MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
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}
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multiclass T_ZV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID HvxQR:$src1, HvxVR:$src2),
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(MI HvxQR:$src1, HvxVR:$src2)>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2),
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(MI HvxQR:$src1, HvxVR:$src2)>;
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}
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multiclass T_R_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID IntRegs:$src1),
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(MI IntRegs:$src1)>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
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(MI IntRegs:$src1)>;
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}
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multiclass T_ZZ_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID HvxQR:$src1, HvxQR:$src2),
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(MI HvxQR:$src1, HvxQR:$src2)>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxQR:$src2),
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(MI HvxQR:$src1, HvxQR:$src2)>;
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}
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multiclass T_VVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3),
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(MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
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imm:$src3),
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(MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
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}
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multiclass T_VVVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4),
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(MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
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HvxVR:$src3, imm:$src4),
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(MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
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}
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multiclass T_WVVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
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def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4),
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(MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
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def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
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HvxVR:$src3, imm:$src4),
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(MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
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}
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def : T_R_pat <S6_vsplatrbp, int_hexagon_S6_vsplatrbp>;
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def : T_PP_pat <M6_vabsdiffb, int_hexagon_M6_vabsdiffb>;
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def : T_PP_pat <M6_vabsdiffub, int_hexagon_M6_vabsdiffub>;
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def : T_PP_pat <S6_vtrunehb_ppp, int_hexagon_S6_vtrunehb_ppp>;
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def : T_PP_pat <S6_vtrunohb_ppp, int_hexagon_S6_vtrunohb_ppp>;
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defm : T_VR_HVX_gen_pat <V6_vlsrb, int_hexagon_V6_vlsrb>;
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defm : T_VR_HVX_gen_pat <V6_vmpyiwub, int_hexagon_V6_vmpyiwub>;
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defm : T_VVL_HVX_gen_pat <V6_vasrwuhrndsat, int_hexagon_V6_vasrwuhrndsat>;
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defm : T_VVL_HVX_gen_pat <V6_vasruwuhrndsat, int_hexagon_V6_vasruwuhrndsat>;
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defm : T_VVL_HVX_gen_pat <V6_vasrhbsat, int_hexagon_V6_vasrhbsat>;
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defm : T_VVL_HVX_gen_pat <V6_vlutvvb_nm, int_hexagon_V6_vlutvvb_nm>;
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defm : T_VVL_HVX_gen_pat <V6_vlutvwh_nm, int_hexagon_V6_vlutvwh_nm>;
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defm : T_VV_HVX_gen_pat <V6_vrounduwuh, int_hexagon_V6_vrounduwuh>;
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defm : T_VV_HVX_gen_pat <V6_vrounduhub, int_hexagon_V6_vrounduhub>;
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defm : T_VV_HVX_gen_pat <V6_vadduwsat, int_hexagon_V6_vadduwsat>;
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defm : T_VV_HVX_gen_pat <V6_vsubuwsat, int_hexagon_V6_vsubuwsat>;
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defm : T_VV_HVX_gen_pat <V6_vaddbsat, int_hexagon_V6_vaddbsat>;
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defm : T_VV_HVX_gen_pat <V6_vsubbsat, int_hexagon_V6_vsubbsat>;
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defm : T_VV_HVX_gen_pat <V6_vaddububb_sat, int_hexagon_V6_vaddububb_sat>;
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defm : T_VV_HVX_gen_pat <V6_vsubububb_sat, int_hexagon_V6_vsubububb_sat>;
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defm : T_VV_HVX_gen_pat <V6_vmpyewuh_64, int_hexagon_V6_vmpyewuh_64>;
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defm : T_VV_HVX_gen_pat <V6_vmaxb, int_hexagon_V6_vmaxb>;
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defm : T_VV_HVX_gen_pat <V6_vminb, int_hexagon_V6_vminb>;
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defm : T_VV_HVX_gen_pat <V6_vsatuwuh, int_hexagon_V6_vsatuwuh>;
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defm : T_VV_HVX_gen_pat <V6_vaddclbw, int_hexagon_V6_vaddclbw>;
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defm : T_VV_HVX_gen_pat <V6_vaddclbh, int_hexagon_V6_vaddclbh>;
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defm : T_WW_HVX_gen_pat <V6_vadduwsat_dv, int_hexagon_V6_vadduwsat_dv>;
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defm : T_WW_HVX_gen_pat <V6_vsubuwsat_dv, int_hexagon_V6_vsubuwsat_dv>;
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defm : T_WW_HVX_gen_pat <V6_vaddbsat_dv, int_hexagon_V6_vaddbsat_dv>;
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defm : T_WW_HVX_gen_pat <V6_vsubbsat_dv, int_hexagon_V6_vsubbsat_dv>;
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defm : T_WVV_HVX_gen_pat <V6_vaddhw_acc, int_hexagon_V6_vaddhw_acc>;
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defm : T_WVV_HVX_gen_pat <V6_vadduhw_acc, int_hexagon_V6_vadduhw_acc>;
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defm : T_WVV_HVX_gen_pat <V6_vaddubh_acc, int_hexagon_V6_vaddubh_acc>;
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defm : T_WVV_HVX_gen_pat <V6_vmpyowh_64_acc, int_hexagon_V6_vmpyowh_64_acc>;
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defm : T_WR_HVX_gen_pat <V6_vmpauhb, int_hexagon_V6_vmpauhb>;
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defm : T_WWR_HVX_gen_pat <V6_vmpauhb_acc, int_hexagon_V6_vmpauhb_acc>;
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defm : T_VVR_HVX_gen_pat <V6_vmpyiwub_acc, int_hexagon_V6_vmpyiwub_acc>;
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defm : T_ZR_HVX_gen_pat <V6_vandnqrt, int_hexagon_V6_vandnqrt>;
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defm : T_VZR_HVX_gen_pat <V6_vandnqrt_acc, int_hexagon_V6_vandnqrt_acc>;
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defm : T_ZV_HVX_gen_pat <V6_vandvqv, int_hexagon_V6_vandvqv>;
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defm : T_ZV_HVX_gen_pat <V6_vandvnqv, int_hexagon_V6_vandvnqv>;
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defm : T_R_HVX_gen_pat <V6_pred_scalar2v2, int_hexagon_V6_pred_scalar2v2>;
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defm : T_R_HVX_gen_pat <V6_lvsplath, int_hexagon_V6_lvsplath>;
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defm : T_R_HVX_gen_pat <V6_lvsplatb, int_hexagon_V6_lvsplatb>;
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defm : T_ZZ_HVX_gen_pat <V6_shuffeqw, int_hexagon_V6_shuffeqw>;
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defm : T_ZZ_HVX_gen_pat <V6_shuffeqh, int_hexagon_V6_shuffeqh>;
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defm : T_VVI_HVX_gen_pat <V6_vlutvvbi, int_hexagon_V6_vlutvvbi>;
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defm : T_VVI_HVX_gen_pat <V6_vlutvwhi, int_hexagon_V6_vlutvwhi>;
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defm : T_VVVI_HVX_gen_pat <V6_vlutvvb_oracci, int_hexagon_V6_vlutvvb_oracci>;
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defm : T_WVVI_HVX_gen_pat <V6_vlutvwh_oracci, int_hexagon_V6_vlutvwh_oracci>;
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