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727 lines
26 KiB
C++
727 lines
26 KiB
C++
//===- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements NewValueJump pass in Hexagon.
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// Ideally, we should merge this as a Peephole pass prior to register
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// allocation, but because we have a spill in between the feeder and new value
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// jump instructions, we are forced to write after register allocation.
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// Having said that, we should re-attempt to pull this earlier at some point
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// in future.
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// The basic approach looks for sequence of predicated jump, compare instruciton
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// that genereates the predicate and, the feeder to the predicate. Once it finds
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// all, it collapses compare and jump instruction into a new value jump
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// intstructions.
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//
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//===----------------------------------------------------------------------===//
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#include "Hexagon.h"
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#include "HexagonInstrInfo.h"
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#include "HexagonRegisterInfo.h"
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#include "HexagonSubtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/BranchProbability.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <cstdint>
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#include <iterator>
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using namespace llvm;
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#define DEBUG_TYPE "hexagon-nvj"
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STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
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static cl::opt<int> DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden,
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cl::desc("Maximum number of predicated jumps to be converted to "
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"New Value Jump"));
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static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
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cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable New Value Jumps"));
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namespace llvm {
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FunctionPass *createHexagonNewValueJump();
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void initializeHexagonNewValueJumpPass(PassRegistry&);
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} // end namespace llvm
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namespace {
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struct HexagonNewValueJump : public MachineFunctionPass {
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static char ID;
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HexagonNewValueJump() : MachineFunctionPass(ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<MachineBranchProbabilityInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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StringRef getPassName() const override { return "Hexagon NewValueJump"; }
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bool runOnMachineFunction(MachineFunction &Fn) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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private:
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const HexagonInstrInfo *QII;
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const HexagonRegisterInfo *QRI;
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/// A handle to the branch probability pass.
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const MachineBranchProbabilityInfo *MBPI;
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bool isNewValueJumpCandidate(const MachineInstr &MI) const;
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};
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} // end anonymous namespace
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char HexagonNewValueJump::ID = 0;
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INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj",
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"Hexagon NewValueJump", false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
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INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj",
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"Hexagon NewValueJump", false, false)
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// We have identified this II could be feeder to NVJ,
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// verify that it can be.
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static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
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const TargetRegisterInfo *TRI,
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MachineBasicBlock::iterator II,
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MachineBasicBlock::iterator end,
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MachineBasicBlock::iterator skip,
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MachineFunction &MF) {
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// Predicated instruction can not be feeder to NVJ.
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if (QII->isPredicated(*II))
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return false;
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// Bail out if feederReg is a paired register (double regs in
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// our case). One would think that we can check to see if a given
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// register cmpReg1 or cmpReg2 is a sub register of feederReg
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// using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
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// before the callsite of this function
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// But we can not as it comes in the following fashion.
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// %d0 = Hexagon_S2_lsr_r_p killed %d0, killed %r2
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// %r0 = KILL %r0, implicit killed %d0
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// %p0 = CMPEQri killed %r0, 0
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// Hence, we need to check if it's a KILL instruction.
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if (II->getOpcode() == TargetOpcode::KILL)
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return false;
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if (II->isImplicitDef())
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return false;
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if (QII->isSolo(*II))
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return false;
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if (QII->isFloat(*II))
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return false;
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// Make sure that the (unique) def operand is a register from IntRegs.
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bool HadDef = false;
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for (const MachineOperand &Op : II->operands()) {
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if (!Op.isReg() || !Op.isDef())
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continue;
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if (HadDef)
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return false;
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HadDef = true;
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if (!Hexagon::IntRegsRegClass.contains(Op.getReg()))
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return false;
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}
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assert(HadDef);
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// Make sure there is no 'def' or 'use' of any of the uses of
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// feeder insn between its definition, this MI and jump, jmpInst
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// skipping compare, cmpInst.
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// Here's the example.
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// r21=memub(r22+r24<<#0)
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// p0 = cmp.eq(r21, #0)
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// r4=memub(r3+r21<<#0)
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// if (p0.new) jump:t .LBB29_45
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// Without this check, it will be converted into
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// r4=memub(r3+r21<<#0)
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// r21=memub(r22+r24<<#0)
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// p0 = cmp.eq(r21, #0)
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// if (p0.new) jump:t .LBB29_45
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// and result WAR hazards if converted to New Value Jump.
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for (unsigned i = 0; i < II->getNumOperands(); ++i) {
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if (II->getOperand(i).isReg() &&
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(II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
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MachineBasicBlock::iterator localII = II;
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++localII;
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unsigned Reg = II->getOperand(i).getReg();
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for (MachineBasicBlock::iterator localBegin = localII; localBegin != end;
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++localBegin) {
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if (localBegin == skip)
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continue;
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// Check for Subregisters too.
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if (localBegin->modifiesRegister(Reg, TRI) ||
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localBegin->readsRegister(Reg, TRI))
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return false;
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}
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}
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}
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return true;
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}
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// These are the common checks that need to performed
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// to determine if
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// 1. compare instruction can be moved before jump.
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// 2. feeder to the compare instruction can be moved before jump.
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static bool commonChecksToProhibitNewValueJump(bool afterRA,
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MachineBasicBlock::iterator MII) {
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// If store in path, bail out.
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if (MII->mayStore())
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return false;
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// if call in path, bail out.
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if (MII->isCall())
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return false;
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// if NVJ is running prior to RA, do the following checks.
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if (!afterRA) {
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// The following Target Opcode instructions are spurious
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// to new value jump. If they are in the path, bail out.
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// KILL sets kill flag on the opcode. It also sets up a
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// single register, out of pair.
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// %d0 = S2_lsr_r_p killed %d0, killed %r2
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// %r0 = KILL %r0, implicit killed %d0
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// %p0 = C2_cmpeqi killed %r0, 0
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// PHI can be anything after RA.
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// COPY can remateriaze things in between feeder, compare and nvj.
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if (MII->getOpcode() == TargetOpcode::KILL ||
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MII->getOpcode() == TargetOpcode::PHI ||
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MII->getOpcode() == TargetOpcode::COPY)
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return false;
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// The following pseudo Hexagon instructions sets "use" and "def"
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// of registers by individual passes in the backend. At this time,
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// we don't know the scope of usage and definitions of these
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// instructions.
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if (MII->getOpcode() == Hexagon::LDriw_pred ||
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MII->getOpcode() == Hexagon::STriw_pred)
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return false;
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}
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return true;
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}
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static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
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const TargetRegisterInfo *TRI,
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MachineBasicBlock::iterator II,
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unsigned pReg,
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bool secondReg,
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bool optLocation,
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MachineBasicBlock::iterator end,
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MachineFunction &MF) {
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MachineInstr &MI = *II;
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// If the second operand of the compare is an imm, make sure it's in the
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// range specified by the arch.
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if (!secondReg) {
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const MachineOperand &Op2 = MI.getOperand(2);
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if (!Op2.isImm())
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return false;
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int64_t v = Op2.getImm();
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bool Valid = false;
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switch (MI.getOpcode()) {
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case Hexagon::C2_cmpeqi:
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case Hexagon::C4_cmpneqi:
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case Hexagon::C2_cmpgti:
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case Hexagon::C4_cmpltei:
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Valid = (isUInt<5>(v) || v == -1);
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break;
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case Hexagon::C2_cmpgtui:
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case Hexagon::C4_cmplteui:
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Valid = isUInt<5>(v);
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break;
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case Hexagon::S2_tstbit_i:
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case Hexagon::S4_ntstbit_i:
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Valid = (v == 0);
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break;
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}
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if (!Valid)
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return false;
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}
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unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning.
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cmpReg1 = MI.getOperand(1).getReg();
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if (secondReg) {
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cmpOp2 = MI.getOperand(2).getReg();
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// If the same register appears as both operands, we cannot generate a new
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// value compare. Only one operand may use the .new suffix.
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if (cmpReg1 == cmpOp2)
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return false;
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// Make sure that the second register is not from COPY
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// at machine code level, we don't need this, but if we decide
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// to move new value jump prior to RA, we would be needing this.
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MachineRegisterInfo &MRI = MF.getRegInfo();
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if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
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MachineInstr *def = MRI.getVRegDef(cmpOp2);
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if (def->getOpcode() == TargetOpcode::COPY)
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return false;
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}
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}
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// Walk the instructions after the compare (predicate def) to the jump,
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// and satisfy the following conditions.
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++II;
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for (MachineBasicBlock::iterator localII = II; localII != end; ++localII) {
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if (localII->isDebugInstr())
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continue;
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// Check 1.
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// If "common" checks fail, bail out.
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if (!commonChecksToProhibitNewValueJump(optLocation, localII))
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return false;
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// Check 2.
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// If there is a def or use of predicate (result of compare), bail out.
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if (localII->modifiesRegister(pReg, TRI) ||
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localII->readsRegister(pReg, TRI))
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return false;
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// Check 3.
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// If there is a def of any of the use of the compare (operands of compare),
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// bail out.
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// Eg.
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// p0 = cmp.eq(r2, r0)
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// r2 = r4
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// if (p0.new) jump:t .LBB28_3
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if (localII->modifiesRegister(cmpReg1, TRI) ||
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(secondReg && localII->modifiesRegister(cmpOp2, TRI)))
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return false;
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}
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return true;
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}
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// Given a compare operator, return a matching New Value Jump compare operator.
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// Make sure that MI here is included in isNewValueJumpCandidate.
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static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
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bool secondRegNewified,
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MachineBasicBlock *jmpTarget,
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const MachineBranchProbabilityInfo
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*MBPI) {
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bool taken = false;
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MachineBasicBlock *Src = MI->getParent();
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const BranchProbability Prediction =
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MBPI->getEdgeProbability(Src, jmpTarget);
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if (Prediction >= BranchProbability(1,2))
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taken = true;
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switch (MI->getOpcode()) {
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case Hexagon::C2_cmpeq:
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return taken ? Hexagon::J4_cmpeq_t_jumpnv_t
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: Hexagon::J4_cmpeq_t_jumpnv_nt;
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case Hexagon::C2_cmpeqi:
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if (reg >= 0)
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return taken ? Hexagon::J4_cmpeqi_t_jumpnv_t
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: Hexagon::J4_cmpeqi_t_jumpnv_nt;
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return taken ? Hexagon::J4_cmpeqn1_t_jumpnv_t
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: Hexagon::J4_cmpeqn1_t_jumpnv_nt;
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case Hexagon::C4_cmpneqi:
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if (reg >= 0)
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return taken ? Hexagon::J4_cmpeqi_f_jumpnv_t
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: Hexagon::J4_cmpeqi_f_jumpnv_nt;
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return taken ? Hexagon::J4_cmpeqn1_f_jumpnv_t :
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Hexagon::J4_cmpeqn1_f_jumpnv_nt;
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case Hexagon::C2_cmpgt:
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if (secondRegNewified)
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return taken ? Hexagon::J4_cmplt_t_jumpnv_t
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: Hexagon::J4_cmplt_t_jumpnv_nt;
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return taken ? Hexagon::J4_cmpgt_t_jumpnv_t
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: Hexagon::J4_cmpgt_t_jumpnv_nt;
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case Hexagon::C2_cmpgti:
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if (reg >= 0)
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return taken ? Hexagon::J4_cmpgti_t_jumpnv_t
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: Hexagon::J4_cmpgti_t_jumpnv_nt;
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return taken ? Hexagon::J4_cmpgtn1_t_jumpnv_t
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: Hexagon::J4_cmpgtn1_t_jumpnv_nt;
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case Hexagon::C2_cmpgtu:
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if (secondRegNewified)
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return taken ? Hexagon::J4_cmpltu_t_jumpnv_t
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: Hexagon::J4_cmpltu_t_jumpnv_nt;
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return taken ? Hexagon::J4_cmpgtu_t_jumpnv_t
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: Hexagon::J4_cmpgtu_t_jumpnv_nt;
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case Hexagon::C2_cmpgtui:
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return taken ? Hexagon::J4_cmpgtui_t_jumpnv_t
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: Hexagon::J4_cmpgtui_t_jumpnv_nt;
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case Hexagon::C4_cmpneq:
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return taken ? Hexagon::J4_cmpeq_f_jumpnv_t
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: Hexagon::J4_cmpeq_f_jumpnv_nt;
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case Hexagon::C4_cmplte:
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if (secondRegNewified)
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return taken ? Hexagon::J4_cmplt_f_jumpnv_t
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: Hexagon::J4_cmplt_f_jumpnv_nt;
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return taken ? Hexagon::J4_cmpgt_f_jumpnv_t
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: Hexagon::J4_cmpgt_f_jumpnv_nt;
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case Hexagon::C4_cmplteu:
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if (secondRegNewified)
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return taken ? Hexagon::J4_cmpltu_f_jumpnv_t
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: Hexagon::J4_cmpltu_f_jumpnv_nt;
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return taken ? Hexagon::J4_cmpgtu_f_jumpnv_t
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: Hexagon::J4_cmpgtu_f_jumpnv_nt;
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case Hexagon::C4_cmpltei:
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if (reg >= 0)
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return taken ? Hexagon::J4_cmpgti_f_jumpnv_t
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: Hexagon::J4_cmpgti_f_jumpnv_nt;
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return taken ? Hexagon::J4_cmpgtn1_f_jumpnv_t
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: Hexagon::J4_cmpgtn1_f_jumpnv_nt;
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case Hexagon::C4_cmplteui:
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return taken ? Hexagon::J4_cmpgtui_f_jumpnv_t
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: Hexagon::J4_cmpgtui_f_jumpnv_nt;
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default:
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llvm_unreachable("Could not find matching New Value Jump instruction.");
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}
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// return *some value* to avoid compiler warning
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return 0;
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}
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bool HexagonNewValueJump::isNewValueJumpCandidate(
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const MachineInstr &MI) const {
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switch (MI.getOpcode()) {
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case Hexagon::C2_cmpeq:
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case Hexagon::C2_cmpeqi:
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case Hexagon::C2_cmpgt:
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case Hexagon::C2_cmpgti:
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case Hexagon::C2_cmpgtu:
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case Hexagon::C2_cmpgtui:
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case Hexagon::C4_cmpneq:
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case Hexagon::C4_cmpneqi:
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case Hexagon::C4_cmplte:
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case Hexagon::C4_cmplteu:
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case Hexagon::C4_cmpltei:
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case Hexagon::C4_cmplteui:
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return true;
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default:
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return false;
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}
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}
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bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
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LLVM_DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
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<< "********** Function: " << MF.getName() << "\n");
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if (skipFunction(MF.getFunction()))
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return false;
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// If we move NewValueJump before register allocation we'll need live variable
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// analysis here too.
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QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
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QRI = static_cast<const HexagonRegisterInfo *>(
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MF.getSubtarget().getRegisterInfo());
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MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
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if (DisableNewValueJumps ||
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!MF.getSubtarget<HexagonSubtarget>().useNewValueJumps())
|
|
return false;
|
|
|
|
int nvjCount = DbgNVJCount;
|
|
int nvjGenerated = 0;
|
|
|
|
// Loop through all the bb's of the function
|
|
for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
|
|
MBBb != MBBe; ++MBBb) {
|
|
MachineBasicBlock *MBB = &*MBBb;
|
|
|
|
LLVM_DEBUG(dbgs() << "** dumping bb ** " << MBB->getNumber() << "\n");
|
|
LLVM_DEBUG(MBB->dump());
|
|
LLVM_DEBUG(dbgs() << "\n"
|
|
<< "********** dumping instr bottom up **********\n");
|
|
bool foundJump = false;
|
|
bool foundCompare = false;
|
|
bool invertPredicate = false;
|
|
unsigned predReg = 0; // predicate reg of the jump.
|
|
unsigned cmpReg1 = 0;
|
|
int cmpOp2 = 0;
|
|
MachineBasicBlock::iterator jmpPos;
|
|
MachineBasicBlock::iterator cmpPos;
|
|
MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr;
|
|
MachineBasicBlock *jmpTarget = nullptr;
|
|
bool afterRA = false;
|
|
bool isSecondOpReg = false;
|
|
bool isSecondOpNewified = false;
|
|
// Traverse the basic block - bottom up
|
|
for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
|
|
MII != E;) {
|
|
MachineInstr &MI = *--MII;
|
|
if (MI.isDebugInstr()) {
|
|
continue;
|
|
}
|
|
|
|
if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
|
|
break;
|
|
|
|
LLVM_DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n");
|
|
|
|
if (!foundJump && (MI.getOpcode() == Hexagon::J2_jumpt ||
|
|
MI.getOpcode() == Hexagon::J2_jumptpt ||
|
|
MI.getOpcode() == Hexagon::J2_jumpf ||
|
|
MI.getOpcode() == Hexagon::J2_jumpfpt ||
|
|
MI.getOpcode() == Hexagon::J2_jumptnewpt ||
|
|
MI.getOpcode() == Hexagon::J2_jumptnew ||
|
|
MI.getOpcode() == Hexagon::J2_jumpfnewpt ||
|
|
MI.getOpcode() == Hexagon::J2_jumpfnew)) {
|
|
// This is where you would insert your compare and
|
|
// instr that feeds compare
|
|
jmpPos = MII;
|
|
jmpInstr = &MI;
|
|
predReg = MI.getOperand(0).getReg();
|
|
afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
|
|
|
|
// If ifconverter had not messed up with the kill flags of the
|
|
// operands, the following check on the kill flag would suffice.
|
|
// if(!jmpInstr->getOperand(0).isKill()) break;
|
|
|
|
// This predicate register is live out of BB
|
|
// this would only work if we can actually use Live
|
|
// variable analysis on phy regs - but LLVM does not
|
|
// provide LV analysis on phys regs.
|
|
//if(LVs.isLiveOut(predReg, *MBB)) break;
|
|
|
|
// Get all the successors of this block - which will always
|
|
// be 2. Check if the predicate register is live-in in those
|
|
// successor. If yes, we can not delete the predicate -
|
|
// I am doing this only because LLVM does not provide LiveOut
|
|
// at the BB level.
|
|
bool predLive = false;
|
|
for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
|
|
SIE = MBB->succ_end();
|
|
SI != SIE; ++SI) {
|
|
MachineBasicBlock *succMBB = *SI;
|
|
if (succMBB->isLiveIn(predReg))
|
|
predLive = true;
|
|
}
|
|
if (predLive)
|
|
break;
|
|
|
|
if (!MI.getOperand(1).isMBB())
|
|
continue;
|
|
jmpTarget = MI.getOperand(1).getMBB();
|
|
foundJump = true;
|
|
if (MI.getOpcode() == Hexagon::J2_jumpf ||
|
|
MI.getOpcode() == Hexagon::J2_jumpfnewpt ||
|
|
MI.getOpcode() == Hexagon::J2_jumpfnew) {
|
|
invertPredicate = true;
|
|
}
|
|
continue;
|
|
}
|
|
|
|
// No new value jump if there is a barrier. A barrier has to be in its
|
|
// own packet. A barrier has zero operands. We conservatively bail out
|
|
// here if we see any instruction with zero operands.
|
|
if (foundJump && MI.getNumOperands() == 0)
|
|
break;
|
|
|
|
if (foundJump && !foundCompare && MI.getOperand(0).isReg() &&
|
|
MI.getOperand(0).getReg() == predReg) {
|
|
// Not all compares can be new value compare. Arch Spec: 7.6.1.1
|
|
if (isNewValueJumpCandidate(MI)) {
|
|
assert(
|
|
(MI.getDesc().isCompare()) &&
|
|
"Only compare instruction can be collapsed into New Value Jump");
|
|
isSecondOpReg = MI.getOperand(2).isReg();
|
|
|
|
if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
|
|
afterRA, jmpPos, MF))
|
|
break;
|
|
|
|
cmpInstr = &MI;
|
|
cmpPos = MII;
|
|
foundCompare = true;
|
|
|
|
// We need cmpReg1 and cmpOp2(imm or reg) while building
|
|
// new value jump instruction.
|
|
cmpReg1 = MI.getOperand(1).getReg();
|
|
|
|
if (isSecondOpReg)
|
|
cmpOp2 = MI.getOperand(2).getReg();
|
|
else
|
|
cmpOp2 = MI.getOperand(2).getImm();
|
|
continue;
|
|
}
|
|
}
|
|
|
|
if (foundCompare && foundJump) {
|
|
// If "common" checks fail, bail out on this BB.
|
|
if (!commonChecksToProhibitNewValueJump(afterRA, MII))
|
|
break;
|
|
|
|
bool foundFeeder = false;
|
|
MachineBasicBlock::iterator feederPos = MII;
|
|
if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() &&
|
|
(MI.getOperand(0).getReg() == cmpReg1 ||
|
|
(isSecondOpReg &&
|
|
MI.getOperand(0).getReg() == (unsigned)cmpOp2))) {
|
|
|
|
unsigned feederReg = MI.getOperand(0).getReg();
|
|
|
|
// First try to see if we can get the feeder from the first operand
|
|
// of the compare. If we can not, and if secondOpReg is true
|
|
// (second operand of the compare is also register), try that one.
|
|
// TODO: Try to come up with some heuristic to figure out which
|
|
// feeder would benefit.
|
|
|
|
if (feederReg == cmpReg1) {
|
|
if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) {
|
|
if (!isSecondOpReg)
|
|
break;
|
|
else
|
|
continue;
|
|
} else
|
|
foundFeeder = true;
|
|
}
|
|
|
|
if (!foundFeeder && isSecondOpReg && feederReg == (unsigned)cmpOp2)
|
|
if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF))
|
|
break;
|
|
|
|
if (isSecondOpReg) {
|
|
// In case of CMPLT, or CMPLTU, or EQ with the second register
|
|
// to newify, swap the operands.
|
|
unsigned COp = cmpInstr->getOpcode();
|
|
if ((COp == Hexagon::C2_cmpeq || COp == Hexagon::C4_cmpneq) &&
|
|
(feederReg == (unsigned)cmpOp2)) {
|
|
unsigned tmp = cmpReg1;
|
|
cmpReg1 = cmpOp2;
|
|
cmpOp2 = tmp;
|
|
}
|
|
|
|
// Now we have swapped the operands, all we need to check is,
|
|
// if the second operand (after swap) is the feeder.
|
|
// And if it is, make a note.
|
|
if (feederReg == (unsigned)cmpOp2)
|
|
isSecondOpNewified = true;
|
|
}
|
|
|
|
// Now that we are moving feeder close the jump,
|
|
// make sure we are respecting the kill values of
|
|
// the operands of the feeder.
|
|
|
|
auto TransferKills = [jmpPos,cmpPos] (MachineInstr &MI) {
|
|
for (MachineOperand &MO : MI.operands()) {
|
|
if (!MO.isReg() || !MO.isUse())
|
|
continue;
|
|
unsigned UseR = MO.getReg();
|
|
for (auto I = std::next(MI.getIterator()); I != jmpPos; ++I) {
|
|
if (I == cmpPos)
|
|
continue;
|
|
for (MachineOperand &Op : I->operands()) {
|
|
if (!Op.isReg() || !Op.isUse() || !Op.isKill())
|
|
continue;
|
|
if (Op.getReg() != UseR)
|
|
continue;
|
|
// We found that there is kill of a use register
|
|
// Set up a kill flag on the register
|
|
Op.setIsKill(false);
|
|
MO.setIsKill(true);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
};
|
|
|
|
TransferKills(*feederPos);
|
|
TransferKills(*cmpPos);
|
|
bool MO1IsKill = cmpPos->killsRegister(cmpReg1, QRI);
|
|
bool MO2IsKill = isSecondOpReg && cmpPos->killsRegister(cmpOp2, QRI);
|
|
|
|
MBB->splice(jmpPos, MI.getParent(), MI);
|
|
MBB->splice(jmpPos, MI.getParent(), cmpInstr);
|
|
DebugLoc dl = MI.getDebugLoc();
|
|
MachineInstr *NewMI;
|
|
|
|
assert((isNewValueJumpCandidate(*cmpInstr)) &&
|
|
"This compare is not a New Value Jump candidate.");
|
|
unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
|
|
isSecondOpNewified,
|
|
jmpTarget, MBPI);
|
|
if (invertPredicate)
|
|
opc = QII->getInvertedPredicatedOpcode(opc);
|
|
|
|
if (isSecondOpReg)
|
|
NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc))
|
|
.addReg(cmpReg1, getKillRegState(MO1IsKill))
|
|
.addReg(cmpOp2, getKillRegState(MO2IsKill))
|
|
.addMBB(jmpTarget);
|
|
|
|
else
|
|
NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc))
|
|
.addReg(cmpReg1, getKillRegState(MO1IsKill))
|
|
.addImm(cmpOp2)
|
|
.addMBB(jmpTarget);
|
|
|
|
assert(NewMI && "New Value Jump Instruction Not created!");
|
|
(void)NewMI;
|
|
if (cmpInstr->getOperand(0).isReg() &&
|
|
cmpInstr->getOperand(0).isKill())
|
|
cmpInstr->getOperand(0).setIsKill(false);
|
|
if (cmpInstr->getOperand(1).isReg() &&
|
|
cmpInstr->getOperand(1).isKill())
|
|
cmpInstr->getOperand(1).setIsKill(false);
|
|
cmpInstr->eraseFromParent();
|
|
jmpInstr->eraseFromParent();
|
|
++nvjGenerated;
|
|
++NumNVJGenerated;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
FunctionPass *llvm::createHexagonNewValueJump() {
|
|
return new HexagonNewValueJump();
|
|
}
|