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to reflect the new license. These used slightly different spellings that defeated my regular expressions. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351648
71 lines
2.9 KiB
C++
71 lines
2.9 KiB
C++
//===- NVPTXInstrInfo.h - NVPTX Instruction Information----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the NVPTX implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXINSTRINFO_H
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#define LLVM_LIB_TARGET_NVPTX_NVPTXINSTRINFO_H
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#include "NVPTX.h"
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#include "NVPTXRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "NVPTXGenInstrInfo.inc"
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namespace llvm {
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class NVPTXInstrInfo : public NVPTXGenInstrInfo {
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const NVPTXRegisterInfo RegInfo;
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virtual void anchor();
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public:
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explicit NVPTXInstrInfo();
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const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
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/* The following virtual functions are used in register allocation.
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* They are not implemented because the existing interface and the logic
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* at the caller side do not work for the elementized vector load and store.
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*
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* virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
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* int &FrameIndex) const;
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* virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
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* int &FrameIndex) const;
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* virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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* MachineBasicBlock::iterator MBBI,
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* unsigned SrcReg, bool isKill, int FrameIndex,
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* const TargetRegisterClass *RC) const;
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* virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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* MachineBasicBlock::iterator MBBI,
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* unsigned DestReg, int FrameIndex,
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* const TargetRegisterClass *RC) const;
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*/
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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// Branch analysis.
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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};
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} // namespace llvm
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#endif
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