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https://github.com/RPCS3/llvm-mirror.git
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156 lines
5.0 KiB
LLVM
156 lines
5.0 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vpaddi8:
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;CHECK: vpadd.i8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vpaddi16:
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;CHECK: vpadd.i16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vpaddi32:
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;CHECK: vpadd.i32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = call <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
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ret <2 x i32> %tmp3
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}
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define <2 x float> @vpaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK: vpaddf32:
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;CHECK: vpadd.f32
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
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ret <2 x float> %tmp3
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}
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declare <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
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define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind {
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;CHECK: vpaddls8:
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;CHECK: vpaddl.s8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind {
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;CHECK: vpaddls16:
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;CHECK: vpaddl.s16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind {
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;CHECK: vpaddls32:
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;CHECK: vpaddl.s32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32> %tmp1)
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ret <1 x i64> %tmp2
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}
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define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind {
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;CHECK: vpaddlu8:
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;CHECK: vpaddl.u8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind {
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;CHECK: vpaddlu16:
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;CHECK: vpaddl.u16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind {
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;CHECK: vpaddlu32:
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;CHECK: vpaddl.u32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32> %tmp1)
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ret <1 x i64> %tmp2
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}
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define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind {
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;CHECK: vpaddlQs8:
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;CHECK: vpaddl.s8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = call <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8> %tmp1)
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind {
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;CHECK: vpaddlQs16:
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;CHECK: vpaddl.s16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16> %tmp1)
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ret <4 x i32> %tmp2
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}
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define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind {
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;CHECK: vpaddlQs32:
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;CHECK: vpaddl.s32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32> %tmp1)
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ret <2 x i64> %tmp2
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}
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define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind {
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;CHECK: vpaddlQu8:
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;CHECK: vpaddl.u8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> %tmp1)
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind {
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;CHECK: vpaddlQu16:
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;CHECK: vpaddl.u16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %tmp1)
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ret <4 x i32> %tmp2
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}
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define <2 x i64> @vpaddlQu32(<4 x i32>* %A) nounwind {
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;CHECK: vpaddlQu32:
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;CHECK: vpaddl.u32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %tmp1)
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ret <2 x i64> %tmp2
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}
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declare <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16>) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16>) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32>) nounwind readnone
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