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llvm-mirror/test/CodeGen/MIR/X86/missing-implicit-operand.mir
Alex Lorenz 5694297a85 MIR Tests: Add liveins and successors to make tests pass with machine verifier.
This commit adds the liveins and successors properties to machine basic blocks
in some of the MIR tests to ensure that the tests will pass when the MIR parser
will run the machine verifier after initializing a machine function.

llvm-svn: 243124
2015-07-24 17:36:55 +00:00

42 lines
981 B
YAML

# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that the MIR parser reports an error when an instruction
# is missing one of its implicit register operands.
--- |
define i32 @foo(i32* %p) {
entry:
%a = load i32, i32* %p
%0 = icmp sle i32 %a, 10
br i1 %0, label %less, label %exit
less:
ret i32 0
exit:
ret i32 %a
}
...
---
name: foo
body:
- id: 0
name: entry
successors: [ '%bb.1.less', '%bb.2.exit' ]
instructions:
- '%eax = MOV32rm %rdi, 1, _, 0, _'
- 'CMP32ri8 %eax, 10, implicit-def %eflags'
# CHECK: [[@LINE+1]]:24: missing implicit register operand 'implicit %eflags'
- 'JG_1 %bb.2.exit'
- id: 1
name: less
instructions:
- '%eax = MOV32r0 implicit-def %eflags'
- id: 2
name: exit
instructions:
- 'RETQ %eax'
...