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45d6ddee89
As discussed in D11886, this patch moves the SSE/AVX vector blend folding to instcombiner from PerformINTRINSIC_WO_CHAINCombine (which allows us to remove this completely). InstCombiner already had partial support for this, I just had to add support for zero (ConstantAggregateZero) masks and also the case where both selection inputs were the same (allowing us to ignore the mask). I also moved all the relevant combine tests into InstCombine/blend_x86.ll Differential Revision: http://reviews.llvm.org/D11934 llvm-svn: 244723
61 lines
1.8 KiB
LLVM
61 lines
1.8 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx | FileCheck %s
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define <4 x double> @test_x86_avx_blend_pd_256(<4 x double> %a0) {
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%1 = call <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double> %a0, <4 x double> %a0, i32 7)
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ret <4 x double> %1
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}
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; CHECK-LABEL: test_x86_avx_blend_pd_256
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; CHECK-NOT: vblendpd
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; CHECK: ret
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define <8 x float> @test_x86_avx_blend_ps_256(<8 x float> %a0) {
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%1 = call <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float> %a0, <8 x float> %a0, i32 7)
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ret <8 x float> %1
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}
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; CHECK-LABEL: test_x86_avx_blend_ps_256
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; CHECK-NOT: vblendps
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; CHECK: ret
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define <4 x double> @test2_x86_avx_blend_pd_256(<4 x double> %a0, <4 x double> %a1) {
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%1 = call <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double> %a0, <4 x double> %a1, i32 0)
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ret <4 x double> %1
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}
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; CHECK-LABEL: test2_x86_avx_blend_pd_256
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; CHECK-NOT: vblendpd
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; CHECK: ret
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define <8 x float> @test2_x86_avx_blend_ps_256(<8 x float> %a0, <8 x float> %a1) {
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%1 = call <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float> %a0, <8 x float> %a1, i32 0)
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ret <8 x float> %1
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}
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; CHECK-LABEL: test2_x86_avx_blend_ps_256
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; CHECK-NOT: vblendps
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; CHECK: ret
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define <4 x double> @test3_x86_avx_blend_pd_256(<4 x double> %a0, <4 x double> %a1) {
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%1 = call <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double> %a0, <4 x double> %a1, i32 -1)
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ret <4 x double> %1
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}
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; CHECK-LABEL: test3_x86_avx_blend_pd_256
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; CHECK-NOT: vblendpd
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; CHECK: ret
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define <8 x float> @test3_x86_avx_blend_ps_256(<8 x float> %a0, <8 x float> %a1) {
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%1 = call <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float> %a0, <8 x float> %a1, i32 -1)
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ret <8 x float> %1
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}
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; CHECK-LABEL: test3_x86_avx_blend_ps_256
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; CHECK-NOT: vblendps
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; CHECK: ret
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declare <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double>, <4 x double>, i32)
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declare <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float>, <8 x float>, i32)
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