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c2664c73ba
This adds the minimum necessary to support codegen for simple ALU operations on RV32. Prolog and epilog insertion, support for memory operations etc etc follow in future patches. Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is reviewed and lands. Differential Revision: https://reviews.llvm.org/D29933 llvm-svn: 316188
36 lines
1021 B
Plaintext
36 lines
1021 B
Plaintext
;===- ./lib/Target/RISCV/LLVMBuild.txt -------------------------*- Conf -*--===;
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;
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; The LLVM Compiler Infrastructure
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;
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; This file is distributed under the University of Illinois Open Source
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; License. See LICENSE.TXT for details.
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;
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;===------------------------------------------------------------------------===;
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;
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; This is an LLVMBuild description file for the components in this subdirectory.
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;
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; For more information on the LLVMBuild system, please see:
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;
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; http://llvm.org/docs/LLVMBuild.html
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;
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;===------------------------------------------------------------------------===;
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[common]
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subdirectories = AsmParser Disassembler InstPrinter TargetInfo MCTargetDesc
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[component_0]
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type = TargetGroup
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name = RISCV
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parent = Target
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has_asmparser = 1
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has_asmprinter = 1
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has_disassembler = 1
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[component_1]
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type = Library
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name = RISCVCodeGen
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parent = RISCV
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required_libraries = AsmPrinter Core CodeGen MC RISCVAsmPrinter RISCVDesc
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RISCVInfo SelectionDAG Support Target
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add_to_library_groups = RISCV
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