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60693dacec
some of the latency computation logic out of the SDNode ScheduleDAG code into a TargetInstrItineraries helper method to help with this. llvm-svn: 59761
100 lines
3.4 KiB
C++
100 lines
3.4 KiB
C++
//===-- llvm/Target/TargetInstrItineraries.h - Scheduling -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the structures used for instruction itineraries and
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// states. This is used by schedulers to determine instruction states and
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// latencies.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETINSTRITINERARIES_H
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#define LLVM_TARGET_TARGETINSTRITINERARIES_H
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namespace llvm {
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//===----------------------------------------------------------------------===//
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/// Instruction stage - These values represent a step in the execution of an
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/// instruction. The latency represents the number of discrete time slots used
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/// need to complete the stage. Units represent the choice of functional units
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/// that can be used to complete the stage. Eg. IntUnit1, IntUnit2.
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///
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struct InstrStage {
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unsigned Cycles; ///< Length of stage in machine cycles
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unsigned Units; ///< Choice of functional units
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};
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//===----------------------------------------------------------------------===//
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/// Instruction itinerary - An itinerary represents a sequential series of steps
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/// required to complete an instruction. Itineraries are represented as
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/// sequences of instruction stages.
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///
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struct InstrItinerary {
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unsigned First; ///< Index of first stage in itinerary
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unsigned Last; ///< Index of last + 1 stage in itinerary
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};
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//===----------------------------------------------------------------------===//
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/// Instruction itinerary Data - Itinerary data supplied by a subtarget to be
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/// used by a target.
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///
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struct InstrItineraryData {
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const InstrStage *Stages; ///< Array of stages selected
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const InstrItinerary *Itineratries; ///< Array of itineraries selected
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/// Ctors.
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///
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InstrItineraryData() : Stages(0), Itineratries(0) {}
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InstrItineraryData(const InstrStage *S, const InstrItinerary *I)
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: Stages(S), Itineratries(I) {}
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/// isEmpty - Returns true if there are no itineraries.
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///
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bool isEmpty() const { return Itineratries == 0; }
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/// begin - Return the first stage of the itinerary.
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///
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const InstrStage *begin(unsigned ItinClassIndx) const {
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unsigned StageIdx = Itineratries[ItinClassIndx].First;
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return Stages + StageIdx;
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}
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/// end - Return the last+1 stage of the itinerary.
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///
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const InstrStage *end(unsigned ItinClassIndx) const {
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unsigned StageIdx = Itineratries[ItinClassIndx].Last;
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return Stages + StageIdx;
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}
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/// getLatency - Return the scheduling latency of the given class. A
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/// simple latency value for an instruction is an over-simplification
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/// for some architectures, but it's a reasonable first approximation.
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///
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unsigned getLatency(unsigned ItinClassIndx) const {
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// If the target doesn't provide latency information, use a simple
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// non-zero default value for all instructions.
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if (isEmpty())
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return 1;
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// Just sum the cycle count for each stage.
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unsigned Latency = 0;
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for (const InstrStage *IS = begin(ItinClassIndx), *E = end(ItinClassIndx);
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IS != E; ++IS)
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Latency += IS->Cycles;
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return Latency;
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}
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};
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} // End llvm namespace
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#endif
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