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3ace682c82
Some instructions like memory reads/writes are executed asynchronously, so we need to insert S_WAITCNT instructions to block before accessing their results. Previously we have just inserted S_WAITCNT instructions after each async instruction, this patch fixes this and adds a prober insertion pass. Patch by: Christian König Tested-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> llvm-svn: 172846
51 lines
1.4 KiB
C++
51 lines
1.4 KiB
C++
//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#ifndef AMDGPU_H
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#define AMDGPU_H
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#include "AMDGPUTargetMachine.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class FunctionPass;
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class AMDGPUTargetMachine;
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// R600 Passes
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FunctionPass* createR600KernelParametersPass(const DataLayout *TD);
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FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
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// SI Passes
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FunctionPass *createSIAnnotateControlFlowPass();
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FunctionPass *createSIAssignInterpRegsPass(TargetMachine &tm);
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FunctionPass *createSILowerControlFlowPass(TargetMachine &tm);
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FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
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FunctionPass *createSILowerLiteralConstantsPass(TargetMachine &tm);
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FunctionPass *createSIInsertWaits(TargetMachine &tm);
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// Passes common to R600 and SI
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Pass *createAMDGPUStructurizeCFGPass();
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FunctionPass *createAMDGPUConvertToISAPass(TargetMachine &tm);
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} // End namespace llvm
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namespace ShaderType {
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enum Type {
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PIXEL = 0,
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VERTEX = 1,
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GEOMETRY = 2,
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COMPUTE = 3
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};
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}
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#endif // AMDGPU_H
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