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08d311e69e
This intrinsics should be shift by immediate, but gcc allows any i32 scalar and clang needs to match that. So we try to detect the non-constant case and move the data from an integer register to an MMX register. Previously this was done by creating a v2i32 build_vector and bitcast in SelectionDAGBuilder. This had to be done early since v2i32 isn't a legal type. The bitcast+build_vector would be DAG combined to X86ISD::MMX_MOVW2D which isel will turn into a GPR->MMX MOVD. This commit just moves the whole thing to lowering and emits the X86ISD::MMX_MOVW2D directly to avoid the illegal type. The test changes just seem to be due to nodes being linearized in a different order. llvm-svn: 372535
138 lines
4.1 KiB
LLVM
138 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X64
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define i32 @t0(i64 %x) nounwind {
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; X86-LABEL: t0:
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; X86: # %bb.0: # %entry
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; X86-NEXT: pshufw $238, {{[0-9]+}}(%esp), %mm0 # mm0 = mem[2,3,2,3]
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; X86-NEXT: movd %mm0, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: t0:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movq %rdi, %mm0
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; X64-NEXT: pshufw $238, %mm0, %mm0 # mm0 = mm0[2,3,2,3]
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; X64-NEXT: movd %mm0, %eax
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; X64-NEXT: retq
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entry:
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%0 = bitcast i64 %x to <4 x i16>
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%1 = bitcast <4 x i16> %0 to x86_mmx
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%2 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %1, i8 -18)
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%3 = bitcast x86_mmx %2 to <4 x i16>
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%4 = bitcast <4 x i16> %3 to <1 x i64>
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%5 = extractelement <1 x i64> %4, i32 0
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%6 = bitcast i64 %5 to <2 x i32>
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%7 = extractelement <2 x i32> %6, i32 0
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ret i32 %7
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}
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define i64 @t1(i64 %x, i32 %n) nounwind {
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; X86-LABEL: t1:
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; X86: # %bb.0: # %entry
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; X86-NEXT: pushl %ebp
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; X86-NEXT: movl %esp, %ebp
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; X86-NEXT: andl $-8, %esp
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; X86-NEXT: subl $8, %esp
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; X86-NEXT: movq 8(%ebp), %mm0
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; X86-NEXT: movd 16(%ebp), %mm1
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; X86-NEXT: psllq %mm1, %mm0
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; X86-NEXT: movq %mm0, (%esp)
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; X86-NEXT: movl (%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl %ebp, %esp
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; X86-NEXT: popl %ebp
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; X86-NEXT: retl
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;
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; X64-LABEL: t1:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movq %rdi, %mm0
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; X64-NEXT: movd %esi, %mm1
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; X64-NEXT: psllq %mm1, %mm0
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; X64-NEXT: movq %mm0, %rax
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; X64-NEXT: retq
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entry:
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%0 = bitcast i64 %x to x86_mmx
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%1 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %0, i32 %n)
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%2 = bitcast x86_mmx %1 to i64
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ret i64 %2
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}
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define i64 @t2(i64 %x, i32 %n, i32 %w) nounwind {
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; X86-LABEL: t2:
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; X86: # %bb.0: # %entry
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; X86-NEXT: pushl %ebp
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; X86-NEXT: movl %esp, %ebp
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; X86-NEXT: andl $-8, %esp
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; X86-NEXT: subl $8, %esp
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; X86-NEXT: movd 20(%ebp), %mm0
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; X86-NEXT: movd 16(%ebp), %mm1
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; X86-NEXT: psllq %mm1, %mm0
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; X86-NEXT: por 8(%ebp), %mm0
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; X86-NEXT: movq %mm0, (%esp)
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; X86-NEXT: movl (%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl %ebp, %esp
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; X86-NEXT: popl %ebp
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; X86-NEXT: retl
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;
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; X64-LABEL: t2:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movd %edx, %mm0
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; X64-NEXT: movd %esi, %mm1
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; X64-NEXT: psllq %mm1, %mm0
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; X64-NEXT: movq %rdi, %mm1
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; X64-NEXT: por %mm0, %mm1
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; X64-NEXT: movq %mm1, %rax
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; X64-NEXT: retq
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entry:
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%0 = insertelement <2 x i32> undef, i32 %w, i32 0
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%1 = insertelement <2 x i32> %0, i32 0, i32 1
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%2 = bitcast <2 x i32> %1 to x86_mmx
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%3 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %2, i32 %n)
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%4 = bitcast i64 %x to x86_mmx
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%5 = tail call x86_mmx @llvm.x86.mmx.por(x86_mmx %4, x86_mmx %3)
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%6 = bitcast x86_mmx %5 to i64
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ret i64 %6
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}
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define i64 @t3(<1 x i64>* %y, i32* %n) nounwind {
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; X86-LABEL: t3:
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; X86: # %bb.0: # %entry
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; X86-NEXT: pushl %ebp
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; X86-NEXT: movl %esp, %ebp
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; X86-NEXT: andl $-8, %esp
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; X86-NEXT: subl $8, %esp
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; X86-NEXT: movl 12(%ebp), %eax
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; X86-NEXT: movl 8(%ebp), %ecx
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; X86-NEXT: movq (%ecx), %mm0
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; X86-NEXT: movd (%eax), %mm1
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; X86-NEXT: psllq %mm1, %mm0
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; X86-NEXT: movq %mm0, (%esp)
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; X86-NEXT: movl (%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl %ebp, %esp
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; X86-NEXT: popl %ebp
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; X86-NEXT: retl
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;
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; X64-LABEL: t3:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movq (%rdi), %mm0
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; X64-NEXT: movd (%rsi), %mm1
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; X64-NEXT: psllq %mm1, %mm0
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; X64-NEXT: movq %mm0, %rax
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; X64-NEXT: retq
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entry:
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%0 = bitcast <1 x i64>* %y to x86_mmx*
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%1 = load x86_mmx, x86_mmx* %0, align 8
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%2 = load i32, i32* %n, align 4
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%3 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %1, i32 %2)
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%4 = bitcast x86_mmx %3 to i64
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ret i64 %4
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}
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declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8)
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declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32)
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declare x86_mmx @llvm.x86.mmx.por(x86_mmx, x86_mmx)
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