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d654e7d40c
Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
29 lines
933 B
LLVM
29 lines
933 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=i686 | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
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; Combine BSWAP (lowered to rolw 8) with a second rotate.
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; This test checks for combining rotates with inconsistent constant value types.
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define i16 @combine_bswap_rotate(i16 %a0) {
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; X86-LABEL: combine_bswap_rotate:
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; X86: # %bb.0:
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; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: rolw $9, %ax
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; X86-NEXT: retl
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;
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; X64-LABEL: combine_bswap_rotate:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: rolw $9, %ax
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; X64-NEXT: # kill: def $ax killed $ax killed $eax
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; X64-NEXT: retq
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%1 = call i16 @llvm.bswap.i16(i16 %a0)
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%2 = shl i16 %1, 1
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%3 = lshr i16 %1, 15
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%4 = or i16 %2, %3
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ret i16 %4
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}
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declare i16 @llvm.bswap.i16(i16)
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