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38e5713f51
Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon Reviewed By: RKSimon Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60228 llvm-svn: 357802
64 lines
2.2 KiB
YAML
64 lines
2.2 KiB
YAML
# RUN: llc -mtriple=x86_64-- -run-pass=simple-register-coalescing -run-pass=regallocbasic -run-pass=virtregrewriter -late-remat-update-threshold=0 %s -o - | FileCheck %s
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#
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# PR40061: %t2 = %t1 is rematerialized and %t1 is added into toBeUpdated set
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# to postpone its live interval update. After the rematerialization, the live
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# interval of %t1 is larger than necessary. Then %t1 is merged into %t3 and %t1
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# gets removed. After the merge, %t3 contains live interval larger than
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# necessary. Because %t3 is not in toBeUpdated set so its live interval is not
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# updated after register coalescing, and it will break some assumption in
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# regalloc. This test wants to check the live interval is up-to-date after
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# register coalescing.
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#
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# To prevent the test from taking effect only in assert enabled mode, we want
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# to achieve the test goal without dumping regalloc trace. We add strong hint
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# to allocate both %t1 and %t2 to $rax register. If the %t1's live interval is
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# not shrinked properly after register coalescing, %t1 and %t2 will not be
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# both allocated to $rax because of inference, and we utilize the fact to
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# achieve the test goal. But note that the assumption only holds when we use
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# regallocbasic instead of greedy because greedy can update the live interval
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# in the process of splitting.
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#
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# CHECK-LABEL: name: foo
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# CHECK: bb.0.entry:
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# CHECK: $rax = MOV64ri32 -11
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# CHECK: bb.1:
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# CHECK: $rax = MOV64ri32 -11
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# CHECK: $rax = ADD64ri8 killed renamable $rax, 5
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# CHECK: CMP64ri8 renamable $rax
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# CHECK: RET 0, $rax
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# CHECK: bb.2:
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# CHECK: $rax = ADD64ri8 killed renamable $rax, 10
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# CHECK: bb.3:
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# CHECK: RET 0, $rax
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---
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name: foo
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body: |
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bb.0.entry:
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successors: %bb.1(0x15555555), %bb.2(0x6aaaaaab)
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%t1:gr64 = MOV64ri32 -11
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CMP64ri8 %t1, 1, implicit-def $eflags
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JCC_1 %bb.2, 4, implicit killed $eflags
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JMP_1 %bb.1
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bb.1:
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successors: %bb.1(0x80000000)
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%t2:gr64 = COPY %t1
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%t2:gr64 = ADD64ri8 %t2, 5, implicit-def $eflags
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$rax = COPY %t2
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CMP64ri8 %t2, 1, implicit-def $eflags
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JCC_1 %bb.1, 4, implicit killed $eflags
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RET 0, $rax
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bb.2:
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successors: %bb.3(0x80000000)
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%t3:gr64 = COPY %t1
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%t3:gr64 = ADD64ri8 %t3, 10, implicit-def $eflags
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bb.3:
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$rax = COPY %t3
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RET 0, $rax
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...
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