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d654e7d40c
Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
18 lines
783 B
LLVM
18 lines
783 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; REQUIRES: asserts
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s
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define <16 x i8> @PR27973() {
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; CHECK-LABEL: PR27973:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: movq $0, 8(%rdi)
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; CHECK-NEXT: movq $0, (%rdi)
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; CHECK-NEXT: retq
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%t0 = zext <16 x i8> zeroinitializer to <16 x i32>
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%t1 = add nuw nsw <16 x i32> %t0, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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%t2 = lshr <16 x i32> %t1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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%t3 = trunc <16 x i32> %t2 to <16 x i8>
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ret <16 x i8> %t3
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}
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