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bcfbda1501
The instruction is defined to only produce high result if both destinations are the same. We can exploit this to avoid unnecessarily clobbering a register. In order to hide this from register allocation we use a pseudo instruction and expand the result during MCInst creation. Differential Revision: https://reviews.llvm.org/D80500
54 lines
1.9 KiB
LLVM
54 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=haswell | FileCheck %s --check-prefix=HSW
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 | FileCheck %s --check-prefix=ZN
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define void @_Z15uint64_to_asciimPc(i64 %arg) {
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; HSW-LABEL: _Z15uint64_to_asciimPc:
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; HSW: # %bb.0: # %bb
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; HSW-NEXT: movabsq $811296384146066817, %rax # imm = 0xB424DC35095CD81
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; HSW-NEXT: movq %rdi, %rdx
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; HSW-NEXT: mulxq %rax, %rax, %rax
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; HSW-NEXT: shrq $42, %rax
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; HSW-NEXT: imulq $281474977, %rax, %rax # imm = 0x10C6F7A1
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; HSW-NEXT: shrq $20, %rax
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; HSW-NEXT: leal (%rax,%rax,4), %eax
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; HSW-NEXT: addl $5, %eax
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; HSW-NEXT: andl $134217727, %eax # imm = 0x7FFFFFF
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; HSW-NEXT: leal (%rax,%rax,4), %eax
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; HSW-NEXT: shrl $26, %eax
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; HSW-NEXT: orb $48, %al
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; HSW-NEXT: movb %al, (%rax)
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; HSW-NEXT: retq
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;
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; ZN-LABEL: _Z15uint64_to_asciimPc:
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; ZN: # %bb.0: # %bb
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; ZN-NEXT: movabsq $811296384146066817, %rax # imm = 0xB424DC35095CD81
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; ZN-NEXT: movq %rdi, %rdx
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; ZN-NEXT: mulxq %rax, %rax, %rax
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; ZN-NEXT: shrq $42, %rax
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; ZN-NEXT: imulq $281474977, %rax, %rax # imm = 0x10C6F7A1
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; ZN-NEXT: shrq $20, %rax
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; ZN-NEXT: leal 5(%rax,%rax,4), %eax
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; ZN-NEXT: andl $134217727, %eax # imm = 0x7FFFFFF
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; ZN-NEXT: leal (%rax,%rax,4), %eax
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; ZN-NEXT: shrl $26, %eax
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; ZN-NEXT: orb $48, %al
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; ZN-NEXT: movb %al, (%rax)
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; ZN-NEXT: retq
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bb:
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%tmp = udiv i64 %arg, 100000000000000
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%tmp1 = mul nuw nsw i64 %tmp, 281474977
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%tmp2 = lshr i64 %tmp1, 20
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%tmp3 = trunc i64 %tmp2 to i32
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%tmp4 = add nuw nsw i32 %tmp3, 1
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%tmp5 = and i32 %tmp4, 268435455
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%tmp6 = mul nuw nsw i32 %tmp5, 5
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%tmp7 = and i32 %tmp6, 134217727
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%tmp8 = mul nuw nsw i32 %tmp7, 5
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%tmp9 = lshr i32 %tmp8, 26
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%tmp10 = trunc i32 %tmp9 to i8
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%tmp11 = or i8 %tmp10, 48
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store i8 %tmp11, i8* undef, align 1
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ret void
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}
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