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24807ec799
We use the functions that convert to three address to do the conversion, but changing an 8 or 16 bit will cause it to create a virtual register. This can't be done after register allocation where this pass runs. I've switched the pass completely to a white list of instructions that can be converted to LEA instead of a blacklist that was incorrect. This will avoid surprises if we enhance the three address conversion function to include additional instructions in the future. Fixes PR42565. llvm-svn: 365720
38 lines
1.4 KiB
LLVM
38 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=atom | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=atom -filetype=obj -o /dev/null
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define void @HUF_writeCTable_wksp() {
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; CHECK-LABEL: HUF_writeCTable_wksp:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl $2, %eax
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; CHECK-NEXT: movb $-2, %cl
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: .LBB0_1: # %for.body
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: leal 1(%rcx), %edx
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; CHECK-NEXT: movb %dl, (%rax)
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; CHECK-NEXT: movb %cl, (%rax)
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; CHECK-NEXT: leaq 2(%rax), %rax
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; CHECK-NEXT: addb $-2, %cl
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; CHECK-NEXT: jmp .LBB0_1
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entry:
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%indvars.iv8 = phi i64 [ 1, %entry ], [ %indvars.iv.next9.1, %for.body ]
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%0 = trunc i64 %indvars.iv8 to i8
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%conv = sub i8 0, %0
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store i8 %conv, i8* undef, align 1
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%indvars.iv.next9 = add nuw nsw i64 %indvars.iv8, 1
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%1 = trunc i64 %indvars.iv.next9 to i8
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%conv.1 = sub i8 0, %1
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%arrayidx.1 = getelementptr inbounds i8, i8* null, i64 %indvars.iv.next9
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store i8 %conv.1, i8* %arrayidx.1, align 1
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%indvars.iv.next9.1 = add nuw nsw i64 %indvars.iv8, 2
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br i1 false, label %for.end, label %for.body
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for.end: ; preds = %for.body
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ret void
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}
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