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cb2d622c70
We require d/q suffixes on the memory form of these instructions to disambiguate the memory size. We don't require it on the register forms, but need to support parsing both with and without it. Previously we always printed the d/q suffix on the register forms, but it's redundant and inconsistent with gcc and objdump. After this patch we should support the d/q for parsing, but not print it when its unneeded. llvm-svn: 360085
209 lines
9.2 KiB
LLVM
209 lines
9.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X86,SSE,X86-SSE
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; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X86,AVX,X86-AVX,AVX1,X86-AVX1
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; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X86,AVX,X86-AVX,AVX512,X86-AVX512
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-sse2 -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X64,SSE,X64-SSE
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X64,AVX,X64-AVX,AVX1,X64-AVX1
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X64,AVX,X64-AVX,AVX512,X64-AVX512
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define <4 x float> @test_x86_sse_sqrt_ps(<4 x float> %a0) {
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; SSE-LABEL: test_x86_sse_sqrt_ps:
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; SSE: ## %bb.0:
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; SSE-NEXT: sqrtps %xmm0, %xmm0 ## encoding: [0x0f,0x51,0xc0]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX1-LABEL: test_x86_sse_sqrt_ps:
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; AVX1: ## %bb.0:
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; AVX1-NEXT: vsqrtps %xmm0, %xmm0 ## encoding: [0xc5,0xf8,0x51,0xc0]
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; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX512-LABEL: test_x86_sse_sqrt_ps:
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; AVX512: ## %bb.0:
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; AVX512-NEXT: vsqrtps %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf8,0x51,0xc0]
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; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.sqrt.ps(<4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_sqrt_ss(<4 x float> %a0) {
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; SSE-LABEL: test_x86_sse_sqrt_ss:
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; SSE: ## %bb.0:
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; SSE-NEXT: sqrtss %xmm0, %xmm0 ## encoding: [0xf3,0x0f,0x51,0xc0]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX1-LABEL: test_x86_sse_sqrt_ss:
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; AVX1: ## %bb.0:
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; AVX1-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x51,0xc0]
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; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX512-LABEL: test_x86_sse_sqrt_ss:
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; AVX512: ## %bb.0:
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; AVX512-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x51,0xc0]
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; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone
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define void @test_x86_sse_storeu_ps(i8* %a0, <4 x float> %a1) {
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; X86-SSE-LABEL: test_x86_sse_storeu_ps:
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; X86-SSE: ## %bb.0:
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; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
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; X86-SSE-NEXT: movups %xmm0, (%eax) ## encoding: [0x0f,0x11,0x00]
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; X86-SSE-NEXT: retl ## encoding: [0xc3]
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;
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; X86-AVX1-LABEL: test_x86_sse_storeu_ps:
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; X86-AVX1: ## %bb.0:
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; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
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; X86-AVX1-NEXT: vmovups %xmm0, (%eax) ## encoding: [0xc5,0xf8,0x11,0x00]
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; X86-AVX1-NEXT: retl ## encoding: [0xc3]
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;
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; X86-AVX512-LABEL: test_x86_sse_storeu_ps:
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; X86-AVX512: ## %bb.0:
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; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
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; X86-AVX512-NEXT: vmovups %xmm0, (%eax) ## EVEX TO VEX Compression encoding: [0xc5,0xf8,0x11,0x00]
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; X86-AVX512-NEXT: retl ## encoding: [0xc3]
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;
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; X64-SSE-LABEL: test_x86_sse_storeu_ps:
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; X64-SSE: ## %bb.0:
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; X64-SSE-NEXT: movups %xmm0, (%rdi) ## encoding: [0x0f,0x11,0x07]
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; X64-SSE-NEXT: retq ## encoding: [0xc3]
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;
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; X64-AVX1-LABEL: test_x86_sse_storeu_ps:
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; X64-AVX1: ## %bb.0:
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; X64-AVX1-NEXT: vmovups %xmm0, (%rdi) ## encoding: [0xc5,0xf8,0x11,0x07]
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; X64-AVX1-NEXT: retq ## encoding: [0xc3]
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;
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; X64-AVX512-LABEL: test_x86_sse_storeu_ps:
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; X64-AVX512: ## %bb.0:
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; X64-AVX512-NEXT: vmovups %xmm0, (%rdi) ## EVEX TO VEX Compression encoding: [0xc5,0xf8,0x11,0x07]
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; X64-AVX512-NEXT: retq ## encoding: [0xc3]
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call void @llvm.x86.sse.storeu.ps(i8* %a0, <4 x float> %a1)
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ret void
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}
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declare void @llvm.x86.sse.storeu.ps(i8*, <4 x float>) nounwind
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define <4 x float> @test_x86_sse_add_ss(<4 x float> %a0, <4 x float> %a1) {
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; SSE-LABEL: test_x86_sse_add_ss:
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; SSE: ## %bb.0:
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; SSE-NEXT: addss %xmm1, %xmm0 ## encoding: [0xf3,0x0f,0x58,0xc1]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX1-LABEL: test_x86_sse_add_ss:
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; AVX1: ## %bb.0:
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; AVX1-NEXT: vaddss %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x58,0xc1]
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; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX512-LABEL: test_x86_sse_add_ss:
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; AVX512: ## %bb.0:
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; AVX512-NEXT: vaddss %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x58,0xc1]
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; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <4 x float> @llvm.x86.sse.add.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.add.ss(<4 x float>, <4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_sub_ss(<4 x float> %a0, <4 x float> %a1) {
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; SSE-LABEL: test_x86_sse_sub_ss:
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; SSE: ## %bb.0:
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; SSE-NEXT: subss %xmm1, %xmm0 ## encoding: [0xf3,0x0f,0x5c,0xc1]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX1-LABEL: test_x86_sse_sub_ss:
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; AVX1: ## %bb.0:
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; AVX1-NEXT: vsubss %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x5c,0xc1]
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; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX512-LABEL: test_x86_sse_sub_ss:
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; AVX512: ## %bb.0:
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; AVX512-NEXT: vsubss %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x5c,0xc1]
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; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <4 x float> @llvm.x86.sse.sub.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.sub.ss(<4 x float>, <4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_mul_ss(<4 x float> %a0, <4 x float> %a1) {
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; SSE-LABEL: test_x86_sse_mul_ss:
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; SSE: ## %bb.0:
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; SSE-NEXT: mulss %xmm1, %xmm0 ## encoding: [0xf3,0x0f,0x59,0xc1]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX1-LABEL: test_x86_sse_mul_ss:
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; AVX1: ## %bb.0:
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; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x59,0xc1]
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; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX512-LABEL: test_x86_sse_mul_ss:
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; AVX512: ## %bb.0:
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; AVX512-NEXT: vmulss %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x59,0xc1]
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; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <4 x float> @llvm.x86.sse.mul.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.mul.ss(<4 x float>, <4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_div_ss(<4 x float> %a0, <4 x float> %a1) {
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; SSE-LABEL: test_x86_sse_div_ss:
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; SSE: ## %bb.0:
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; SSE-NEXT: divss %xmm1, %xmm0 ## encoding: [0xf3,0x0f,0x5e,0xc1]
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; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX1-LABEL: test_x86_sse_div_ss:
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; AVX1: ## %bb.0:
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; AVX1-NEXT: vdivss %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x5e,0xc1]
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; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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;
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; AVX512-LABEL: test_x86_sse_div_ss:
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; AVX512: ## %bb.0:
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; AVX512-NEXT: vdivss %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x5e,0xc1]
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; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
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%res = call <4 x float> @llvm.x86.sse.div.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.div.ss(<4 x float>, <4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_cvtsi2ss(<4 x float> %a0, i32 %a1) {
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; X86-SSE-LABEL: test_x86_sse_cvtsi2ss:
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; X86-SSE: ## %bb.0:
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; X86-SSE-NEXT: cvtsi2ssl {{[0-9]+}}(%esp), %xmm0 ## encoding: [0xf3,0x0f,0x2a,0x44,0x24,0x04]
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; X86-SSE-NEXT: retl ## encoding: [0xc3]
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;
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; X86-AVX1-LABEL: test_x86_sse_cvtsi2ss:
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; X86-AVX1: ## %bb.0:
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; X86-AVX1-NEXT: vcvtsi2ssl {{[0-9]+}}(%esp), %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x2a,0x44,0x24,0x04]
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; X86-AVX1-NEXT: retl ## encoding: [0xc3]
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;
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; X86-AVX512-LABEL: test_x86_sse_cvtsi2ss:
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; X86-AVX512: ## %bb.0:
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; X86-AVX512-NEXT: vcvtsi2ssl {{[0-9]+}}(%esp), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x2a,0x44,0x24,0x04]
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; X86-AVX512-NEXT: retl ## encoding: [0xc3]
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;
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; X64-SSE-LABEL: test_x86_sse_cvtsi2ss:
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; X64-SSE: ## %bb.0:
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; X64-SSE-NEXT: cvtsi2ss %edi, %xmm0 ## encoding: [0xf3,0x0f,0x2a,0xc7]
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; X64-SSE-NEXT: retq ## encoding: [0xc3]
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;
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; X64-AVX1-LABEL: test_x86_sse_cvtsi2ss:
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; X64-AVX1: ## %bb.0:
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; X64-AVX1-NEXT: vcvtsi2ss %edi, %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x2a,0xc7]
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; X64-AVX1-NEXT: retq ## encoding: [0xc3]
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;
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; X64-AVX512-LABEL: test_x86_sse_cvtsi2ss:
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; X64-AVX512: ## %bb.0:
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; X64-AVX512-NEXT: vcvtsi2ss %edi, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x2a,0xc7]
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; X64-AVX512-NEXT: retq ## encoding: [0xc3]
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%res = call <4 x float> @llvm.x86.sse.cvtsi2ss(<4 x float> %a0, i32 %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.cvtsi2ss(<4 x float>, i32) nounwind readnone
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