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a973c0bd85
When the target option GuaranteedTailCallOpt is specified, calls with the fastcc calling convention will be transformed into tail calls if they are in tail position. This diff adds a new calling convention, tailcc, currently supported only on X86, which behaves the same way as fastcc, except that the GuaranteedTailCallOpt flag does not need to enabled in order to enable tail call optimization. Patch by Dwight Guth <dwight.guth@runtimeverification.com>! Reviewed By: lebedev.ri, paquette, rnk Differential Revision: https://reviews.llvm.org/D67855 llvm-svn: 373976
156 lines
4.4 KiB
LLVM
156 lines
4.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s -check-prefix=X64
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; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s -check-prefix=X32
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; With -tailcallopt, CodeGen guarantees a tail call optimization
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; for all of these.
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declare tailcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4)
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define tailcc i32 @tailcaller(i32 %in1, i32 %in2) nounwind {
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; X64-LABEL: tailcaller:
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; X64: # %bb.0: # %entry
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; X64-NEXT: pushq %rax
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; X64-NEXT: movl %edi, %edx
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; X64-NEXT: movl %esi, %ecx
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; X64-NEXT: popq %rax
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; X64-NEXT: jmp tailcallee # TAILCALL
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;
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; X32-LABEL: tailcaller:
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; X32: # %bb.0: # %entry
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; X32-NEXT: subl $16, %esp
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; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl %edx, {{[0-9]+}}(%esp)
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; X32-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; X32-NEXT: addl $8, %esp
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; X32-NEXT: jmp tailcallee # TAILCALL
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entry:
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%tmp11 = tail call tailcc i32 @tailcallee(i32 %in1, i32 %in2, i32 %in1, i32 %in2)
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ret i32 %tmp11
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}
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declare tailcc i8* @alias_callee()
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define tailcc noalias i8* @noalias_caller() nounwind {
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; X64-LABEL: noalias_caller:
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; X64: # %bb.0:
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; X64-NEXT: pushq %rax
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; X64-NEXT: popq %rax
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; X64-NEXT: jmp alias_callee # TAILCALL
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;
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; X32-LABEL: noalias_caller:
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; X32: # %bb.0:
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; X32-NEXT: jmp alias_callee # TAILCALL
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%p = tail call tailcc i8* @alias_callee()
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ret i8* %p
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}
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declare tailcc noalias i8* @noalias_callee()
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define tailcc i8* @alias_caller() nounwind {
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; X64-LABEL: alias_caller:
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; X64: # %bb.0:
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; X64-NEXT: pushq %rax
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; X64-NEXT: popq %rax
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; X64-NEXT: jmp noalias_callee # TAILCALL
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;
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; X32-LABEL: alias_caller:
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; X32: # %bb.0:
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; X32-NEXT: jmp noalias_callee # TAILCALL
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%p = tail call tailcc noalias i8* @noalias_callee()
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ret i8* %p
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}
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declare tailcc i32 @i32_callee()
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define tailcc i32 @ret_undef() nounwind {
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; X64-LABEL: ret_undef:
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; X64: # %bb.0:
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; X64-NEXT: pushq %rax
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; X64-NEXT: popq %rax
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; X64-NEXT: jmp i32_callee # TAILCALL
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;
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; X32-LABEL: ret_undef:
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; X32: # %bb.0:
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; X32-NEXT: jmp i32_callee # TAILCALL
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%p = tail call tailcc i32 @i32_callee()
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ret i32 undef
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}
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declare tailcc void @does_not_return()
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define tailcc i32 @noret() nounwind {
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; X64-LABEL: noret:
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; X64: # %bb.0:
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; X64-NEXT: pushq %rax
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; X64-NEXT: popq %rax
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; X64-NEXT: jmp does_not_return # TAILCALL
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;
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; X32-LABEL: noret:
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; X32: # %bb.0:
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; X32-NEXT: jmp does_not_return # TAILCALL
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tail call tailcc void @does_not_return()
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unreachable
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}
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define tailcc void @void_test(i32, i32, i32, i32) {
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; X64-LABEL: void_test:
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; X64: # %bb.0: # %entry
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; X64-NEXT: pushq %rax
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; X64-NEXT: .cfi_def_cfa_offset 16
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; X64-NEXT: popq %rax
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; X64-NEXT: .cfi_def_cfa_offset 8
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; X64-NEXT: jmp void_test # TAILCALL
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;
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; X32-LABEL: void_test:
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; X32: # %bb.0: # %entry
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; X32-NEXT: pushl %esi
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; X32-NEXT: .cfi_def_cfa_offset 8
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; X32-NEXT: subl $8, %esp
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; X32-NEXT: .cfi_def_cfa_offset 16
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; X32-NEXT: .cfi_offset %esi, -8
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X32-NEXT: movl %esi, {{[0-9]+}}(%esp)
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; X32-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; X32-NEXT: addl $8, %esp
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; X32-NEXT: .cfi_def_cfa_offset 8
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; X32-NEXT: popl %esi
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; X32-NEXT: .cfi_def_cfa_offset 4
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; X32-NEXT: jmp void_test # TAILCALL
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entry:
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tail call tailcc void @void_test( i32 %0, i32 %1, i32 %2, i32 %3)
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ret void
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}
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define tailcc i1 @i1test(i32, i32, i32, i32) {
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; X64-LABEL: i1test:
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; X64: # %bb.0: # %entry
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; X64-NEXT: pushq %rax
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; X64-NEXT: .cfi_def_cfa_offset 16
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; X64-NEXT: popq %rax
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; X64-NEXT: .cfi_def_cfa_offset 8
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; X64-NEXT: jmp i1test # TAILCALL
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;
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; X32-LABEL: i1test:
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; X32: # %bb.0: # %entry
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; X32-NEXT: pushl %esi
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; X32-NEXT: .cfi_def_cfa_offset 8
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; X32-NEXT: subl $8, %esp
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; X32-NEXT: .cfi_def_cfa_offset 16
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; X32-NEXT: .cfi_offset %esi, -8
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X32-NEXT: movl %esi, {{[0-9]+}}(%esp)
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; X32-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; X32-NEXT: addl $8, %esp
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; X32-NEXT: .cfi_def_cfa_offset 8
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; X32-NEXT: popl %esi
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; X32-NEXT: .cfi_def_cfa_offset 4
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; X32-NEXT: jmp i1test # TAILCALL
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entry:
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%4 = tail call tailcc i1 @i1test( i32 %0, i32 %1, i32 %2, i32 %3)
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ret i1 %4
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}
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