mirror of
https://github.com/RPCS3/llvm-mirror.git
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f63ff65eda
Summary: Defines instruction itineraries for common MIPSR6 instructions. Patch by Simon Dardis. Reviewers: vkalintiris Subscribers: MatzeB, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D17198 llvm-svn: 263229
460 lines
24 KiB
TableGen
460 lines
24 KiB
TableGen
//===-- MipsSchedule.td - Mips Scheduling Definitions ------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Functional units across Mips chips sets. Based on GCC/Mips backend files.
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//===----------------------------------------------------------------------===//
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def ALU : FuncUnit;
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def IMULDIV : FuncUnit;
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//===----------------------------------------------------------------------===//
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// Instruction Itinerary classes used for Mips
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//===----------------------------------------------------------------------===//
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// IIM16Alu is a placeholder class for most MIPS16 instructions.
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def IIM16Alu : InstrItinClass;
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def IIPseudo : InstrItinClass;
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def II_ABS : InstrItinClass;
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def II_ADDI : InstrItinClass;
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def II_ADDIU : InstrItinClass;
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def II_ADDIUPC : InstrItinClass;
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def II_ADDU : InstrItinClass;
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def II_ADD_D : InstrItinClass;
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def II_ADD_S : InstrItinClass;
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def II_ALIGN : InstrItinClass;
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def II_AND : InstrItinClass;
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def II_ANDI : InstrItinClass;
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def II_ALUIPC : InstrItinClass;
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def II_AUI : InstrItinClass;
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def II_AUIPC : InstrItinClass;
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def II_B : InstrItinClass;
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def II_BADDU : InstrItinClass;
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def II_BBIT : InstrItinClass; // bbit[01], bbit[01]32
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def II_BALC : InstrItinClass;
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def II_BC : InstrItinClass;
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def II_BC1F : InstrItinClass;
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def II_BC1FL : InstrItinClass;
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def II_BC1T : InstrItinClass;
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def II_BC1TL : InstrItinClass;
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def II_BC1CCZ : InstrItinClass;
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def II_BCC : InstrItinClass; // beq and bne
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def II_BCCZ : InstrItinClass; // b[gl][et]z
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def II_BCCC : InstrItinClass; // b<cc>c
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def II_BCCZAL : InstrItinClass; // bgezal and bltzal
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def II_BCCZALS : InstrItinClass; // bgezals and bltzals
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def II_BCCZC : InstrItinClass; // beqzc, bnezc
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def II_BITSWAP : InstrItinClass;
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def II_CEIL : InstrItinClass;
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def II_CFC1 : InstrItinClass;
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def II_CLO : InstrItinClass;
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def II_CLZ : InstrItinClass;
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def II_CTC1 : InstrItinClass;
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def II_CVT : InstrItinClass;
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def II_C_CC_D : InstrItinClass; // Any c.<cc>.d instruction
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def II_C_CC_S : InstrItinClass; // Any c.<cc>.s instruction
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def II_DADDIU : InstrItinClass;
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def II_DADDU : InstrItinClass;
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def II_DADD : InstrItinClass;
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def II_DAHI : InstrItinClass;
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def II_DATI : InstrItinClass;
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def II_DAUI : InstrItinClass;
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def II_DALIGN : InstrItinClass;
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def II_DBITSWAP : InstrItinClass;
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def II_DCLO : InstrItinClass;
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def II_DCLZ : InstrItinClass;
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def II_DDIV : InstrItinClass;
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def II_DDIVU : InstrItinClass;
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def II_DIV : InstrItinClass;
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def II_DIVU : InstrItinClass;
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def II_DIV_D : InstrItinClass;
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def II_DIV_S : InstrItinClass;
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def II_DMFC1 : InstrItinClass;
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def II_DMTC1 : InstrItinClass;
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def II_DMOD : InstrItinClass;
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def II_DMODU : InstrItinClass;
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def II_DMUH : InstrItinClass;
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def II_DMUHU : InstrItinClass;
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def II_DMUL : InstrItinClass;
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def II_DMULU : InstrItinClass;
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def II_DMULT : InstrItinClass;
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def II_DMULTU : InstrItinClass;
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def II_DROTR : InstrItinClass;
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def II_DROTR32 : InstrItinClass;
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def II_DROTRV : InstrItinClass;
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def II_DSLL : InstrItinClass;
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def II_DSLL32 : InstrItinClass;
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def II_DSLLV : InstrItinClass;
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def II_DSRA : InstrItinClass;
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def II_DSRA32 : InstrItinClass;
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def II_DSRAV : InstrItinClass;
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def II_DSRL : InstrItinClass;
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def II_DSRL32 : InstrItinClass;
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def II_DSRLV : InstrItinClass;
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def II_DSUBU : InstrItinClass;
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def II_DSUB : InstrItinClass;
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def II_EXT : InstrItinClass; // Any EXT instruction
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def II_FLOOR : InstrItinClass;
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def II_INS : InstrItinClass; // Any INS instruction
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def II_IndirectBranchPseudo : InstrItinClass; // Indirect branch pseudo.
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def II_J : InstrItinClass;
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def II_JAL : InstrItinClass;
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def II_JALR : InstrItinClass;
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def II_JALRC : InstrItinClass;
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def II_JALRS : InstrItinClass;
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def II_JALS : InstrItinClass;
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def II_JIC : InstrItinClass;
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def II_JIALC : InstrItinClass;
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def II_JR : InstrItinClass;
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def II_JRADDIUSP : InstrItinClass;
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def II_JRC : InstrItinClass;
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def II_ReturnPseudo : InstrItinClass; // Return pseudo.
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def II_LB : InstrItinClass;
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def II_LBE : InstrItinClass;
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def II_LBU : InstrItinClass;
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def II_LBUE : InstrItinClass;
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def II_LD : InstrItinClass;
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def II_LDC1 : InstrItinClass;
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def II_LDL : InstrItinClass;
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def II_LDR : InstrItinClass;
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def II_LDPC : InstrItinClass;
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def II_LDXC1 : InstrItinClass;
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def II_LH : InstrItinClass;
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def II_LHE : InstrItinClass;
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def II_LHU : InstrItinClass;
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def II_LHUE : InstrItinClass;
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def II_LUI : InstrItinClass;
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def II_LUXC1 : InstrItinClass;
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def II_LW : InstrItinClass;
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def II_LWE : InstrItinClass;
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def II_LWC1 : InstrItinClass;
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def II_LWL : InstrItinClass;
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def II_LWLE : InstrItinClass;
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def II_LWPC : InstrItinClass;
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def II_LWR : InstrItinClass;
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def II_LWRE : InstrItinClass;
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def II_LWU : InstrItinClass;
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def II_LWUPC : InstrItinClass;
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def II_LWXC1 : InstrItinClass;
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def II_LL : InstrItinClass;
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def II_LLD : InstrItinClass;
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def II_LSA : InstrItinClass;
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def II_DLSA : InstrItinClass;
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def II_MADD : InstrItinClass;
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def II_MADDU : InstrItinClass;
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def II_MADD_D : InstrItinClass;
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def II_MADD_S : InstrItinClass;
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def II_MADDF_D : InstrItinClass;
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def II_MADDF_S : InstrItinClass;
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def II_MFC1 : InstrItinClass;
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def II_MFHC1 : InstrItinClass;
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def II_MFHI_MFLO : InstrItinClass; // mfhi and mflo
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def II_MOD : InstrItinClass;
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def II_MODU : InstrItinClass;
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def II_MOVF : InstrItinClass;
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def II_MOVF_D : InstrItinClass;
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def II_MOVF_S : InstrItinClass;
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def II_MOVN : InstrItinClass;
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def II_MOVN_D : InstrItinClass;
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def II_MOVN_S : InstrItinClass;
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def II_MOVT : InstrItinClass;
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def II_MOVT_D : InstrItinClass;
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def II_MOVT_S : InstrItinClass;
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def II_MOVZ : InstrItinClass;
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def II_MOVZ_D : InstrItinClass;
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def II_MOVZ_S : InstrItinClass;
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def II_MOV_D : InstrItinClass;
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def II_MOV_S : InstrItinClass;
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def II_MSUB : InstrItinClass;
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def II_MSUBU : InstrItinClass;
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def II_MSUB_D : InstrItinClass;
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def II_MSUB_S : InstrItinClass;
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def II_MSUBF_D : InstrItinClass;
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def II_MSUBF_S : InstrItinClass;
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def II_MTC1 : InstrItinClass;
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def II_MTHC1 : InstrItinClass;
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def II_MTHI_MTLO : InstrItinClass; // mthi and mtlo
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def II_MUL : InstrItinClass;
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def II_MUH : InstrItinClass;
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def II_MUHU : InstrItinClass;
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def II_MULU : InstrItinClass;
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def II_MULT : InstrItinClass;
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def II_MULTU : InstrItinClass;
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def II_MUL_D : InstrItinClass;
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def II_MUL_S : InstrItinClass;
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def II_NEG : InstrItinClass;
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def II_NMADD_D : InstrItinClass;
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def II_NMADD_S : InstrItinClass;
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def II_NMSUB_D : InstrItinClass;
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def II_NMSUB_S : InstrItinClass;
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def II_NOR : InstrItinClass;
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def II_OR : InstrItinClass;
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def II_ORI : InstrItinClass;
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def II_POP : InstrItinClass;
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def II_RDHWR : InstrItinClass;
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def II_RESTORE : InstrItinClass;
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def II_ROTR : InstrItinClass;
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def II_ROTRV : InstrItinClass;
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def II_ROUND : InstrItinClass;
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def II_SAVE : InstrItinClass;
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def II_SC : InstrItinClass;
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def II_SCD : InstrItinClass;
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def II_SB : InstrItinClass;
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def II_SBE : InstrItinClass;
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def II_SD : InstrItinClass;
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def II_SDC1 : InstrItinClass;
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def II_SDL : InstrItinClass;
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def II_SDR : InstrItinClass;
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def II_SDXC1 : InstrItinClass;
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def II_SEB : InstrItinClass;
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def II_SEH : InstrItinClass;
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def II_SELCCZ : InstrItinClass;
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def II_SEQ_SNE : InstrItinClass; // seq and sne
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def II_SEQI_SNEI : InstrItinClass; // seqi and snei
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def II_SH : InstrItinClass;
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def II_SHE : InstrItinClass;
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def II_SLL : InstrItinClass;
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def II_SLLV : InstrItinClass;
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def II_SLTI_SLTIU : InstrItinClass; // slti and sltiu
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def II_SLT_SLTU : InstrItinClass; // slt and sltu
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def II_SQRT_D : InstrItinClass;
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def II_SQRT_S : InstrItinClass;
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def II_SRA : InstrItinClass;
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def II_SRAV : InstrItinClass;
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def II_SRL : InstrItinClass;
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def II_SRLV : InstrItinClass;
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def II_SUBU : InstrItinClass;
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def II_SUB_D : InstrItinClass;
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def II_SUB_S : InstrItinClass;
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def II_SUXC1 : InstrItinClass;
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def II_SW : InstrItinClass;
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def II_SWE : InstrItinClass;
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def II_SWC1 : InstrItinClass;
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def II_SWL : InstrItinClass;
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def II_SWLE : InstrItinClass;
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def II_SWR : InstrItinClass;
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def II_SWRE : InstrItinClass;
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def II_SWXC1 : InstrItinClass;
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def II_TRUNC : InstrItinClass;
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def II_WSBH : InstrItinClass;
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def II_XOR : InstrItinClass;
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def II_XORI : InstrItinClass;
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//===----------------------------------------------------------------------===//
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// Mips Generic instruction itineraries.
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//===----------------------------------------------------------------------===//
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def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
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InstrItinData<IIM16Alu , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_ADDI , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_ADDIU , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_ADDIUPC , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_ADDU , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_AUI , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_AND , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_ALUIPC , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_AUIPC , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_ALIGN , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_BADDU , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_BITSWAP , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SLL , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SRA , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SRL , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_ROTR , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SLLV , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SRAV , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SRLV , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_ROTRV , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_CLO , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_CLZ , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DADDIU , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DADDU , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DADD , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DALIGN , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DAHI , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DATI , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DAUI , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DBITSWAP , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DCLO , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DCLZ , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DMOD , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<II_DMODU , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<II_DSLL , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DSRL , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DSRA , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DSLLV , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DSRLV , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DSRAV , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DSUBU , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DSUB , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DROTR , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_DROTRV , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_EXT , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_INS , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_LUI , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_MOVF , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_MOVN , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_MOVN_S , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_MOVN_D , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_MOVT , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_MOVZ , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_NOR , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_OR , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_POP , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_RDHWR , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SUBU , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_XOR , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_ANDI , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_ORI , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_XORI , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_LB , [InstrStage<3, [ALU]>]>,
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InstrItinData<II_LBU , [InstrStage<3, [ALU]>]>,
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InstrItinData<II_LH , [InstrStage<3, [ALU]>]>,
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InstrItinData<II_LHU , [InstrStage<3, [ALU]>]>,
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InstrItinData<II_LW , [InstrStage<3, [ALU]>]>,
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InstrItinData<II_LWPC , [InstrStage<3, [ALU]>]>,
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InstrItinData<II_LWL , [InstrStage<3, [ALU]>]>,
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InstrItinData<II_LWR , [InstrStage<3, [ALU]>]>,
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InstrItinData<II_LWUPC , [InstrStage<3, [ALU]>]>,
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InstrItinData<II_LD , [InstrStage<3, [ALU]>]>,
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InstrItinData<II_LDL , [InstrStage<3, [ALU]>]>,
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InstrItinData<II_LDR , [InstrStage<3, [ALU]>]>,
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InstrItinData<II_LDPC , [InstrStage<3, [ALU]>]>,
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InstrItinData<II_LL , [InstrStage<3, [ALU]>]>,
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InstrItinData<II_LLD , [InstrStage<3, [ALU]>]>,
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InstrItinData<II_RESTORE , [InstrStage<3, [ALU]>]>,
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InstrItinData<II_SB , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SH , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SW , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SWL , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SWR , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SDL , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SDR , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SD , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SAVE , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SELCCZ , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SEQ_SNE , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SEQI_SNEI , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SC , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_SCD , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_B , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_BALC , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_BBIT , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_BC , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_BC1F , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_BC1FL , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_BC1T , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_BC1TL , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_BC1CCZ , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_BCC , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_BCCC , [InstrStage<1, [ALU]>]>,
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|
InstrItinData<II_BCCZ , [InstrStage<1, [ALU]>]>,
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|
InstrItinData<II_BCCZAL , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_BCCZALS , [InstrStage<1, [ALU]>]>,
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|
InstrItinData<II_BCCZC , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_IndirectBranchPseudo, [InstrStage<1, [ALU]>]>,
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|
InstrItinData<II_J , [InstrStage<1, [ALU]>]>,
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|
InstrItinData<II_JAL , [InstrStage<1, [ALU]>]>,
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|
InstrItinData<II_JALR , [InstrStage<1, [ALU]>]>,
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|
InstrItinData<II_JALRC , [InstrStage<1, [ALU]>]>,
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|
InstrItinData<II_JALRS , [InstrStage<1, [ALU]>]>,
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|
InstrItinData<II_JALS , [InstrStage<1, [ALU]>]>,
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|
InstrItinData<II_JIC , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_JIALC , [InstrStage<1, [ALU]>]>,
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|
InstrItinData<II_JR , [InstrStage<1, [ALU]>]>,
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InstrItinData<II_JRADDIUSP , [InstrStage<1, [ALU]>]>,
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|
InstrItinData<II_JRC , [InstrStage<1, [ALU]>]>,
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|
InstrItinData<II_ReturnPseudo , [InstrStage<1, [ALU]>]>,
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|
InstrItinData<II_DMUH , [InstrStage<17, [IMULDIV]>]>,
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|
InstrItinData<II_DMUHU , [InstrStage<17, [IMULDIV]>]>,
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|
InstrItinData<II_DMUL , [InstrStage<17, [IMULDIV]>]>,
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InstrItinData<II_DMULT , [InstrStage<17, [IMULDIV]>]>,
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|
InstrItinData<II_DMULTU , [InstrStage<17, [IMULDIV]>]>,
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|
InstrItinData<II_DMULU , [InstrStage<17, [IMULDIV]>]>,
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|
InstrItinData<II_MADD , [InstrStage<17, [IMULDIV]>]>,
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|
InstrItinData<II_MADDU , [InstrStage<17, [IMULDIV]>]>,
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|
InstrItinData<II_MFHI_MFLO , [InstrStage<1, [IMULDIV]>]>,
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|
InstrItinData<II_MOD , [InstrStage<38, [IMULDIV]>]>,
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|
InstrItinData<II_MODU , [InstrStage<38, [IMULDIV]>]>,
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|
InstrItinData<II_MSUB , [InstrStage<17, [IMULDIV]>]>,
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|
InstrItinData<II_MSUBU , [InstrStage<17, [IMULDIV]>]>,
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|
InstrItinData<II_MTHI_MTLO , [InstrStage<1, [IMULDIV]>]>,
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|
InstrItinData<II_MUH , [InstrStage<17, [IMULDIV]>]>,
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|
InstrItinData<II_MUHU , [InstrStage<17, [IMULDIV]>]>,
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|
InstrItinData<II_MUL , [InstrStage<17, [IMULDIV]>]>,
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|
InstrItinData<II_MULT , [InstrStage<17, [IMULDIV]>]>,
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|
InstrItinData<II_MULTU , [InstrStage<17, [IMULDIV]>]>,
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|
InstrItinData<II_MULU , [InstrStage<17, [IMULDIV]>]>,
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|
InstrItinData<II_MSUB , [InstrStage<17, [IMULDIV]>]>,
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|
InstrItinData<II_MSUBU , [InstrStage<17, [IMULDIV]>]>,
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|
InstrItinData<II_DIV , [InstrStage<38, [IMULDIV]>]>,
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|
InstrItinData<II_DIVU , [InstrStage<38, [IMULDIV]>]>,
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|
InstrItinData<II_DDIV , [InstrStage<38, [IMULDIV]>]>,
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|
InstrItinData<II_DDIVU , [InstrStage<38, [IMULDIV]>]>,
|
|
InstrItinData<II_CEIL , [InstrStage<1, [ALU]>]>,
|
|
InstrItinData<II_CVT , [InstrStage<1, [ALU]>]>,
|
|
InstrItinData<II_ABS , [InstrStage<1, [ALU]>]>,
|
|
InstrItinData<II_FLOOR , [InstrStage<1, [ALU]>]>,
|
|
InstrItinData<II_NEG , [InstrStage<1, [ALU]>]>,
|
|
InstrItinData<II_ROUND , [InstrStage<1, [ALU]>]>,
|
|
InstrItinData<II_TRUNC , [InstrStage<1, [ALU]>]>,
|
|
InstrItinData<II_MOV_D , [InstrStage<2, [ALU]>]>,
|
|
InstrItinData<II_MOV_S , [InstrStage<2, [ALU]>]>,
|
|
InstrItinData<II_CFC1 , [InstrStage<2, [ALU]>]>,
|
|
InstrItinData<II_CTC1 , [InstrStage<2, [ALU]>]>,
|
|
InstrItinData<II_MOVF_D , [InstrStage<2, [ALU]>]>,
|
|
InstrItinData<II_MOVF_S , [InstrStage<2, [ALU]>]>,
|
|
InstrItinData<II_MOVT_D , [InstrStage<2, [ALU]>]>,
|
|
InstrItinData<II_MOVT_S , [InstrStage<2, [ALU]>]>,
|
|
InstrItinData<II_MOVZ_D , [InstrStage<2, [ALU]>]>,
|
|
InstrItinData<II_MOVZ_S , [InstrStage<2, [ALU]>]>,
|
|
InstrItinData<II_C_CC_S , [InstrStage<3, [ALU]>]>,
|
|
InstrItinData<II_C_CC_D , [InstrStage<3, [ALU]>]>,
|
|
InstrItinData<II_ADD_D , [InstrStage<4, [ALU]>]>,
|
|
InstrItinData<II_ADD_S , [InstrStage<4, [ALU]>]>,
|
|
InstrItinData<II_SUB_D , [InstrStage<4, [ALU]>]>,
|
|
InstrItinData<II_SUB_S , [InstrStage<4, [ALU]>]>,
|
|
InstrItinData<II_MUL_S , [InstrStage<7, [ALU]>]>,
|
|
InstrItinData<II_MADD_S , [InstrStage<7, [ALU]>]>,
|
|
InstrItinData<II_MADDF_S , [InstrStage<7, [ALU]>]>,
|
|
InstrItinData<II_MSUB_S , [InstrStage<7, [ALU]>]>,
|
|
InstrItinData<II_MSUBF_S , [InstrStage<7, [ALU]>]>,
|
|
InstrItinData<II_NMADD_S , [InstrStage<7, [ALU]>]>,
|
|
InstrItinData<II_NMSUB_S , [InstrStage<7, [ALU]>]>,
|
|
InstrItinData<II_MUL_D , [InstrStage<8, [ALU]>]>,
|
|
InstrItinData<II_MADD_D , [InstrStage<8, [ALU]>]>,
|
|
InstrItinData<II_MADDF_D , [InstrStage<8, [ALU]>]>,
|
|
InstrItinData<II_MSUB_D , [InstrStage<8, [ALU]>]>,
|
|
InstrItinData<II_MSUBF_D , [InstrStage<8, [ALU]>]>,
|
|
InstrItinData<II_NMADD_D , [InstrStage<8, [ALU]>]>,
|
|
InstrItinData<II_NMSUB_D , [InstrStage<8, [ALU]>]>,
|
|
InstrItinData<II_DIV_S , [InstrStage<23, [ALU]>]>,
|
|
InstrItinData<II_DIV_D , [InstrStage<36, [ALU]>]>,
|
|
InstrItinData<II_SQRT_S , [InstrStage<54, [ALU]>]>,
|
|
InstrItinData<II_SQRT_D , [InstrStage<12, [ALU]>]>,
|
|
InstrItinData<II_LSA , [InstrStage<1, [ALU]>]>,
|
|
InstrItinData<II_DLSA , [InstrStage<1, [ALU]>]>,
|
|
InstrItinData<II_LDC1 , [InstrStage<3, [ALU]>]>,
|
|
InstrItinData<II_LWC1 , [InstrStage<3, [ALU]>]>,
|
|
InstrItinData<II_LDXC1 , [InstrStage<3, [ALU]>]>,
|
|
InstrItinData<II_LWXC1 , [InstrStage<3, [ALU]>]>,
|
|
InstrItinData<II_LUXC1 , [InstrStage<3, [ALU]>]>,
|
|
InstrItinData<II_SDC1 , [InstrStage<1, [ALU]>]>,
|
|
InstrItinData<II_SWC1 , [InstrStage<1, [ALU]>]>,
|
|
InstrItinData<II_SDXC1 , [InstrStage<1, [ALU]>]>,
|
|
InstrItinData<II_SWXC1 , [InstrStage<1, [ALU]>]>,
|
|
InstrItinData<II_SUXC1 , [InstrStage<1, [ALU]>]>,
|
|
InstrItinData<II_DMFC1 , [InstrStage<2, [ALU]>]>,
|
|
InstrItinData<II_DMTC1 , [InstrStage<2, [ALU]>]>,
|
|
InstrItinData<II_MFC1 , [InstrStage<2, [ALU]>]>,
|
|
InstrItinData<II_MTC1 , [InstrStage<2, [ALU]>]>,
|
|
InstrItinData<II_MFHC1 , [InstrStage<2, [ALU]>]>,
|
|
InstrItinData<II_MTHC1 , [InstrStage<2, [ALU]>]>
|
|
]>;
|
|
|
|
include "MipsScheduleP5600.td"
|