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144 lines
4.4 KiB
Plaintext
144 lines
4.4 KiB
Plaintext
Analysing live variables ...
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For BB 0x4d6510(L1Done) :
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Defs:
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In: 0x4d6398(i4)
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Out:
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For BB 0x5ab408(L1Header) :
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Defs: 0x4c6528 0x4d6350(i3) 0x4d6398(i4) 0x4ddf50 0x5ab450(i2)
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In: 0x4d8290(i1) 0x726c68(PhiCp:)
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Out:
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For BB 0x4d8248(Start) :
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Defs: 0x4d8290(i1) 0x726c68(PhiCp:)
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In: 0x4e4690(j) 0x501658(i)
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Out:
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After Backward Pass 0...
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For BB L1Done:
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In: 0x4d6398(i4)
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Out:
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For BB L1Header:
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In: 0x4d8290(i1) 0x726c68(PhiCp:)
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Out: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
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For BB Start:
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In: 0x4e4690(j) 0x501658(i)
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Out: 0x4d8290(i1) 0x726c68(PhiCp:)
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After Backward Pass 1...
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For BB L1Done:
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In: 0x4d6398(i4)
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Out:
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For BB L1Header:
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In: 0x4d8290(i1) 0x726c68(PhiCp:)
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Out: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
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For BB Start:
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In: 0x4e4690(j) 0x501658(i)
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Out: 0x4d8290(i1) 0x726c68(PhiCp:)
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Live Variable Analysis complete!
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======For BB Start: Live var sets for instructions======
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Live var sets before/after instruction nop
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Before: 0x4d8290(i1) 0x726c68(PhiCp:)
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After : 0x4d8290(i1) 0x726c68(PhiCp:)
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Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L1Header)
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Before: 0x4d8290(i1) 0x726c68(PhiCp:)
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After : 0x4d8290(i1) 0x726c68(PhiCp:)
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Live var sets before/after instruction add %reg(val i1) %reg(23) %reg(val PhiCp:)*
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Before: 0x4d8290(i1)
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After : 0x4d8290(i1) 0x726c68(PhiCp:)
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Live var sets before/after instruction add %reg(val i) %reg(val j) %reg(val i1)*
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Before: 0x4e4690(j) 0x501658(i)
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After : 0x4d8290(i1)
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======For BB L1Header: Live var sets for instructions======
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Live var sets before/after instruction nop
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Before: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
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After : 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
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Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L1Header)
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Before: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
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After : 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
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Live var sets before/after instruction nop
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Before: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
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After : 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
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Live var sets before/after instruction bg %ccreg(val 0x4ddf50) %disp(label L1Done)
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Before: 0x4d6398(i4) 0x4d8290(i1) 0x4ddf50 0x726c68(PhiCp:)
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After : 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:)
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Live var sets before/after instruction add %reg(val i4) %reg(23) %reg(val PhiCp:)*
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Before: 0x4d6398(i4) 0x4d8290(i1) 0x4ddf50
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After : 0x4d6398(i4) 0x4d8290(i1) 0x4ddf50 0x726c68(PhiCp:)
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Live var sets before/after instruction subcc %reg(val i4) %reg(val 0x4c6528) %reg(23)* %ccreg(val 0x4ddf50)*
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Before: 0x4c6528 0x4d6398(i4) 0x4d8290(i1)
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After : 0x4d6398(i4) 0x4d8290(i1) 0x4ddf50
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Live var sets before/after instruction setsw 10 %reg(val 0x4c6528)*
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Before: 0x4d6398(i4) 0x4d8290(i1)
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After : 0x4c6528 0x4d6398(i4) 0x4d8290(i1)
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Live var sets before/after instruction add %reg(val i2) %reg(val i3) %reg(val i4)*
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Before: 0x4d6350(i3) 0x4d8290(i1) 0x5ab450(i2)
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After : 0x4d6398(i4) 0x4d8290(i1)
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Live var sets before/after instruction add %reg(val i1) %reg(23) %reg(val i3)*
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Before: 0x4d8290(i1) 0x5ab450(i2)
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After : 0x4d6350(i3) 0x4d8290(i1) 0x5ab450(i2)
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Live var sets before/after instruction add %reg(val PhiCp:) %reg(23) %reg(val i2)*
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Before: 0x4d8290(i1) 0x726c68(PhiCp:)
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After : 0x4d8290(i1) 0x5ab450(i2)
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======For BB L1Done: Live var sets for instructions======
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Live var sets before/after instruction nop
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Before:
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After :
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Live var sets before/after instruction jmpl %reg(22)* 8 %reg(23) Implicit:0x4d6398
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Before: 0x4d6398(i4)
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After :
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Analysing live variables ...
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For BB 0x5ab498(bb0) :
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Defs: 0x4daa90 0x4f2d68 0x4f2df8 0x501768(result)
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In:
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Out:
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After Backward Pass 0...
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For BB bb0:
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In:
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Out:
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Live Variable Analysis complete!
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======For BB bb0: Live var sets for instructions======
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Live var sets before/after instruction nop
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Before:
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After :
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Live var sets before/after instruction jmpl %reg(22)* 8 %reg(23) Implicit:0x501768
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Before: 0x501768(result)
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After :
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Live var sets before/after instruction nop
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Before: 0x501768(result)
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After : 0x501768(result)
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Live var sets before/after instruction call %disp(label PhiTest) Implicit:0x4f2d68 0x4f2df8 0x501768* 0x4daa90*
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Before: 0x4f2d68 0x4f2df8
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After : 0x501768(result)
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Live var sets before/after instruction setsw 17 %reg(val 0x4f2df8)*
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Before: 0x4f2d68
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After : 0x4f2d68 0x4f2df8
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Live var sets before/after instruction setsw 9 %reg(val 0x4f2d68)*
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Before:
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After : 0x4f2d68
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