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dcd7a1bde2
Summary: This hidden option would disable code generation through FastISel by default. It was removed from the available options and from the Fast-ISel tests that required it in order to run the tests. Reviewers: dsanders Subscribers: qcolombet, llvm-commits Differential Revision: http://reviews.llvm.org/D11610 llvm-svn: 243638
35 lines
1.4 KiB
LLVM
35 lines
1.4 KiB
LLVM
; Check that register scavenging spill slot is close to $fp.
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; RUN: llc -march=mipsel -O0 -fast-isel=false < %s | FileCheck %s
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; CHECK: sw ${{.*}}, 8($sp)
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; CHECK: lw ${{.*}}, 8($sp)
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define i32 @main(i32 signext %argc, i8** %argv) #0 {
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entry:
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%retval = alloca i32, align 4
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%argc.addr = alloca i32, align 4
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%argv.addr = alloca i8**, align 4
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%v0 = alloca <16 x i8>, align 16
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%.compoundliteral = alloca <16 x i8>, align 16
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%v1 = alloca <16 x i8>, align 16
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%.compoundliteral1 = alloca <16 x i8>, align 16
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%unused_variable = alloca [16384 x i32], align 4
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%result = alloca <16 x i8>, align 16
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store i32 0, i32* %retval
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store i32 %argc, i32* %argc.addr, align 4
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store i8** %argv, i8*** %argv.addr, align 4
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store <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, <16 x i8>* %.compoundliteral
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%0 = load <16 x i8>, <16 x i8>* %.compoundliteral
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store <16 x i8> %0, <16 x i8>* %v0, align 16
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store <16 x i8> zeroinitializer, <16 x i8>* %.compoundliteral1
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%1 = load <16 x i8>, <16 x i8>* %.compoundliteral1
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store <16 x i8> %1, <16 x i8>* %v1, align 16
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%2 = load <16 x i8>, <16 x i8>* %v0, align 16
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%3 = load <16 x i8>, <16 x i8>* %v1, align 16
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%mul = mul <16 x i8> %2, %3
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store <16 x i8> %mul, <16 x i8>* %result, align 16
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ret i32 0
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}
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attributes #0 = { noinline optnone "no-frame-pointer-elim"="true" }
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