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54ac1d95cd
Previously the patterns didn't have high enough priority and we would only use the GR32 form if the only the upper 32 or 56 bits were zero. Fixes PR23100. llvm-svn: 234075
37 lines
1.0 KiB
LLVM
37 lines
1.0 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
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; rdar://7329206
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; Use sbb x, x to materialize carry bit in a GPR. The value is either
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; all 1's or all 0's.
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define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t1:
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; CHECK: seta %al
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; CHECK: movzbl %al, %eax
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; CHECK: shll $5, %eax
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%0 = icmp ugt i16 %x, 26 ; <i1> [#uses=1]
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%iftmp.1.0 = select i1 %0, i16 32, i16 0 ; <i16> [#uses=1]
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ret i16 %iftmp.1.0
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}
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define zeroext i16 @t2(i16 zeroext %x) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t2:
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; CHECK: sbbl %eax, %eax
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; CHECK: andl $32, %eax
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%0 = icmp ult i16 %x, 26 ; <i1> [#uses=1]
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%iftmp.0.0 = select i1 %0, i16 32, i16 0 ; <i16> [#uses=1]
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ret i16 %iftmp.0.0
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}
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define i64 @t3(i64 %x) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t3:
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; CHECK: sbbq %rax, %rax
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; CHECK: andl $64, %eax
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%0 = icmp ult i64 %x, 18 ; <i1> [#uses=1]
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%iftmp.2.0 = select i1 %0, i64 64, i64 0 ; <i64> [#uses=1]
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ret i64 %iftmp.2.0
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}
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