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ba759cb550
This patch introduces the combine: (C1 shift (A add C2)) -> ((C1 shift C2) shift A) iff A and C2 are both positive If both A and C2 are know to be positive then we can safely split into 2 shifts, permitting the folding of the Inner shift. Fix for the spec benchmark case mentioned by @nadav on PR15141 (assuming we can prove that the inputs as positive). Differential Revision: https://reviews.llvm.org/D26000 llvm-svn: 285696
75 lines
2.4 KiB
LLVM
75 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; This test makes sure that these instructions are properly eliminated.
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;
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; RUN: opt < %s -instcombine -S | FileCheck %s
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define i32 @shl_C1_add_A_C2_i32(i16 %A) {
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; CHECK-LABEL: @shl_C1_add_A_C2_i32(
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; CHECK-NEXT: [[B:%.*]] = zext i16 %A to i32
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; CHECK-NEXT: [[D:%.*]] = shl i32 192, [[B]]
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; CHECK-NEXT: ret i32 [[D]]
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;
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%B = zext i16 %A to i32
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%C = add i32 %B, 5
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%D = shl i32 6, %C
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ret i32 %D
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}
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define i32 @ashr_C1_add_A_C2_i32(i32 %A) {
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; CHECK-LABEL: @ashr_C1_add_A_C2_i32(
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; CHECK-NEXT: ret i32 0
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;
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%B = and i32 %A, 65535
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%C = add i32 %B, 5
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%D = ashr i32 6, %C
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ret i32 %D
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}
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define i32 @lshr_C1_add_A_C2_i32(i32 %A) {
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; CHECK-LABEL: @lshr_C1_add_A_C2_i32(
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; CHECK-NEXT: [[B:%.*]] = and i32 %A, 65535
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; CHECK-NEXT: [[D:%.*]] = shl i32 192, [[B]]
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; CHECK-NEXT: ret i32 [[D]]
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;
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%B = and i32 %A, 65535
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%C = add i32 %B, 5
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%D = shl i32 6, %C
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ret i32 %D
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}
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define <4 x i32> @shl_C1_add_A_C2_v4i32(<4 x i16> %A) {
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; CHECK-LABEL: @shl_C1_add_A_C2_v4i32(
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; CHECK-NEXT: [[B:%.*]] = zext <4 x i16> %A to <4 x i32>
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; CHECK-NEXT: [[D:%.*]] = shl <4 x i32> <i32 6, i32 4, i32 undef, i32 -458752>, [[B]]
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; CHECK-NEXT: ret <4 x i32> [[D]]
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;
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%B = zext <4 x i16> %A to <4 x i32>
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%C = add <4 x i32> %B, <i32 0, i32 1, i32 50, i32 16>
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%D = shl <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %C
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ret <4 x i32> %D
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}
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define <4 x i32> @ashr_C1_add_A_C2_v4i32(<4 x i32> %A) {
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; CHECK-LABEL: @ashr_C1_add_A_C2_v4i32(
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; CHECK-NEXT: [[B:%.*]] = and <4 x i32> %A, <i32 0, i32 15, i32 255, i32 65535>
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; CHECK-NEXT: [[D:%.*]] = ashr <4 x i32> <i32 6, i32 1, i32 undef, i32 -1>, [[B]]
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; CHECK-NEXT: ret <4 x i32> [[D]]
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;
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%B = and <4 x i32> %A, <i32 0, i32 15, i32 255, i32 65535>
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%C = add <4 x i32> %B, <i32 0, i32 1, i32 50, i32 16>
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%D = ashr <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %C
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ret <4 x i32> %D
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}
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define <4 x i32> @lshr_C1_add_A_C2_v4i32(<4 x i32> %A) {
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; CHECK-LABEL: @lshr_C1_add_A_C2_v4i32(
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; CHECK-NEXT: [[B:%.*]] = and <4 x i32> %A, <i32 0, i32 15, i32 255, i32 65535>
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; CHECK-NEXT: [[D:%.*]] = lshr <4 x i32> <i32 6, i32 1, i32 undef, i32 65535>, [[B]]
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; CHECK-NEXT: ret <4 x i32> [[D]]
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;
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%B = and <4 x i32> %A, <i32 0, i32 15, i32 255, i32 65535>
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%C = add <4 x i32> %B, <i32 0, i32 1, i32 50, i32 16>
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%D = lshr <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %C
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ret <4 x i32> %D
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}
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