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https://github.com/RPCS3/llvm-mirror.git
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468 lines
14 KiB
Plaintext
468 lines
14 KiB
Plaintext
Target Independent Opportunities:
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//===---------------------------------------------------------------------===//
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With the recent changes to make the implicit def/use set explicit in
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machineinstrs, we should change the target descriptions for 'call' instructions
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so that the .td files don't list all the call-clobbered registers as implicit
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defs. Instead, these should be added by the code generator (e.g. on the dag).
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This has a number of uses:
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1. PPC32/64 and X86 32/64 can avoid having multiple copies of call instructions
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for their different impdef sets.
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2. Targets with multiple calling convs (e.g. x86) which have different clobber
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sets don't need copies of call instructions.
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3. 'Interprocedural register allocation' can be done to reduce the clobber sets
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of calls.
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//===---------------------------------------------------------------------===//
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Make the PPC branch selector target independant
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//===---------------------------------------------------------------------===//
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Get the C front-end to expand hypot(x,y) -> llvm.sqrt(x*x+y*y) when errno and
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precision don't matter (ffastmath). Misc/mandel will like this. :)
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//===---------------------------------------------------------------------===//
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Solve this DAG isel folding deficiency:
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int X, Y;
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void fn1(void)
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{
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X = X | (Y << 3);
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}
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compiles to
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fn1:
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movl Y, %eax
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shll $3, %eax
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orl X, %eax
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movl %eax, X
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ret
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The problem is the store's chain operand is not the load X but rather
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a TokenFactor of the load X and load Y, which prevents the folding.
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There are two ways to fix this:
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1. The dag combiner can start using alias analysis to realize that y/x
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don't alias, making the store to X not dependent on the load from Y.
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2. The generated isel could be made smarter in the case it can't
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disambiguate the pointers.
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Number 1 is the preferred solution.
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This has been "fixed" by a TableGen hack. But that is a short term workaround
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which will be removed once the proper fix is made.
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//===---------------------------------------------------------------------===//
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On targets with expensive 64-bit multiply, we could LSR this:
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for (i = ...; ++i) {
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x = 1ULL << i;
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into:
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long long tmp = 1;
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for (i = ...; ++i, tmp+=tmp)
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x = tmp;
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This would be a win on ppc32, but not x86 or ppc64.
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//===---------------------------------------------------------------------===//
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Shrink: (setlt (loadi32 P), 0) -> (setlt (loadi8 Phi), 0)
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//===---------------------------------------------------------------------===//
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Reassociate should turn: X*X*X*X -> t=(X*X) (t*t) to eliminate a multiply.
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//===---------------------------------------------------------------------===//
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Interesting? testcase for add/shift/mul reassoc:
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int bar(int x, int y) {
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return x*x*x+y+x*x*x*x*x*y*y*y*y;
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}
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int foo(int z, int n) {
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return bar(z, n) + bar(2*z, 2*n);
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}
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Reassociate should handle the example in GCC PR16157.
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//===---------------------------------------------------------------------===//
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These two functions should generate the same code on big-endian systems:
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int g(int *j,int *l) { return memcmp(j,l,4); }
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int h(int *j, int *l) { return *j - *l; }
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this could be done in SelectionDAGISel.cpp, along with other special cases,
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for 1,2,4,8 bytes.
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//===---------------------------------------------------------------------===//
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It would be nice to revert this patch:
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http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20060213/031986.html
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And teach the dag combiner enough to simplify the code expanded before
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legalize. It seems plausible that this knowledge would let it simplify other
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stuff too.
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//===---------------------------------------------------------------------===//
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For vector types, TargetData.cpp::getTypeInfo() returns alignment that is equal
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to the type size. It works but can be overly conservative as the alignment of
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specific vector types are target dependent.
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//===---------------------------------------------------------------------===//
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We should add 'unaligned load/store' nodes, and produce them from code like
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this:
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v4sf example(float *P) {
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return (v4sf){P[0], P[1], P[2], P[3] };
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}
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//===---------------------------------------------------------------------===//
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We should constant fold vector type casts at the LLVM level, regardless of the
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cast. Currently we cannot fold some casts because we don't have TargetData
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information in the constant folder, so we don't know the endianness of the
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target!
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//===---------------------------------------------------------------------===//
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Add support for conditional increments, and other related patterns. Instead
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of:
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movl 136(%esp), %eax
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cmpl $0, %eax
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je LBB16_2 #cond_next
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LBB16_1: #cond_true
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incl _foo
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LBB16_2: #cond_next
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emit:
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movl _foo, %eax
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cmpl $1, %edi
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sbbl $-1, %eax
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movl %eax, _foo
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//===---------------------------------------------------------------------===//
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Combine: a = sin(x), b = cos(x) into a,b = sincos(x).
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Expand these to calls of sin/cos and stores:
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double sincos(double x, double *sin, double *cos);
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float sincosf(float x, float *sin, float *cos);
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long double sincosl(long double x, long double *sin, long double *cos);
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Doing so could allow SROA of the destination pointers. See also:
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=17687
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//===---------------------------------------------------------------------===//
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Scalar Repl cannot currently promote this testcase to 'ret long cst':
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%struct.X = type { i32, i32 }
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%struct.Y = type { %struct.X }
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define i64 @bar() {
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%retval = alloca %struct.Y, align 8
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%tmp12 = getelementptr %struct.Y* %retval, i32 0, i32 0, i32 0
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store i32 0, i32* %tmp12
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%tmp15 = getelementptr %struct.Y* %retval, i32 0, i32 0, i32 1
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store i32 1, i32* %tmp15
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%retval.upgrd.1 = bitcast %struct.Y* %retval to i64*
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%retval.upgrd.2 = load i64* %retval.upgrd.1
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ret i64 %retval.upgrd.2
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}
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it should be extended to do so.
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//===---------------------------------------------------------------------===//
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-scalarrepl should promote this to be a vector scalar.
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%struct..0anon = type { <4 x float> }
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define void @test1(<4 x float> %V, float* %P) {
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%u = alloca %struct..0anon, align 16
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%tmp = getelementptr %struct..0anon* %u, i32 0, i32 0
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store <4 x float> %V, <4 x float>* %tmp
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%tmp1 = bitcast %struct..0anon* %u to [4 x float]*
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%tmp.upgrd.1 = getelementptr [4 x float]* %tmp1, i32 0, i32 1
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%tmp.upgrd.2 = load float* %tmp.upgrd.1
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%tmp3 = mul float %tmp.upgrd.2, 2.000000e+00
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store float %tmp3, float* %P
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ret void
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}
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//===---------------------------------------------------------------------===//
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Turn this into a single byte store with no load (the other 3 bytes are
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unmodified):
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void %test(uint* %P) {
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%tmp = load uint* %P
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%tmp14 = or uint %tmp, 3305111552
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%tmp15 = and uint %tmp14, 3321888767
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store uint %tmp15, uint* %P
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ret void
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}
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//===---------------------------------------------------------------------===//
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dag/inst combine "clz(x)>>5 -> x==0" for 32-bit x.
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Compile:
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int bar(int x)
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{
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int t = __builtin_clz(x);
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return -(t>>5);
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}
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to:
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_bar: addic r3,r3,-1
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subfe r3,r3,r3
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blr
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//===---------------------------------------------------------------------===//
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Legalize should lower ctlz like this:
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ctlz(x) = popcnt((x-1) & ~x)
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on targets that have popcnt but not ctlz. itanium, what else?
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//===---------------------------------------------------------------------===//
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quantum_sigma_x in 462.libquantum contains the following loop:
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for(i=0; i<reg->size; i++)
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{
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/* Flip the target bit of each basis state */
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reg->node[i].state ^= ((MAX_UNSIGNED) 1 << target);
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}
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Where MAX_UNSIGNED/state is a 64-bit int. On a 32-bit platform it would be just
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so cool to turn it into something like:
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long long Res = ((MAX_UNSIGNED) 1 << target);
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if (target < 32) {
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for(i=0; i<reg->size; i++)
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reg->node[i].state ^= Res & 0xFFFFFFFFULL;
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} else {
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for(i=0; i<reg->size; i++)
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reg->node[i].state ^= Res & 0xFFFFFFFF00000000ULL
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}
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... which would only do one 32-bit XOR per loop iteration instead of two.
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It would also be nice to recognize the reg->size doesn't alias reg->node[i], but
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alas...
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//===---------------------------------------------------------------------===//
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This isn't recognized as bswap by instcombine:
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unsigned int swap_32(unsigned int v) {
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v = ((v & 0x00ff00ffU) << 8) | ((v & 0xff00ff00U) >> 8);
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v = ((v & 0x0000ffffU) << 16) | ((v & 0xffff0000U) >> 16);
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return v;
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}
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Nor is this (yes, it really is bswap):
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unsigned long reverse(unsigned v) {
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unsigned t;
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t = v ^ ((v << 16) | (v >> 16));
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t &= ~0xff0000;
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v = (v << 24) | (v >> 8);
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return v ^ (t >> 8);
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}
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//===---------------------------------------------------------------------===//
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These should turn into single 16-bit (unaligned?) loads on little/big endian
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processors.
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unsigned short read_16_le(const unsigned char *adr) {
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return adr[0] | (adr[1] << 8);
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}
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unsigned short read_16_be(const unsigned char *adr) {
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return (adr[0] << 8) | adr[1];
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}
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//===---------------------------------------------------------------------===//
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-instcombine should handle this transform:
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icmp pred (sdiv X / C1 ), C2
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when X, C1, and C2 are unsigned. Similarly for udiv and signed operands.
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Currently InstCombine avoids this transform but will do it when the signs of
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the operands and the sign of the divide match. See the FIXME in
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InstructionCombining.cpp in the visitSetCondInst method after the switch case
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for Instruction::UDiv (around line 4447) for more details.
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The SingleSource/Benchmarks/Shootout-C++/hash and hash2 tests have examples of
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this construct.
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//===---------------------------------------------------------------------===//
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Instcombine misses several of these cases (see the testcase in the patch):
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http://gcc.gnu.org/ml/gcc-patches/2006-10/msg01519.html
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//===---------------------------------------------------------------------===//
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viterbi speeds up *significantly* if the various "history" related copy loops
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are turned into memcpy calls at the source level. We need a "loops to memcpy"
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pass.
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//===---------------------------------------------------------------------===//
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Consider:
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typedef unsigned U32;
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typedef unsigned long long U64;
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int test (U32 *inst, U64 *regs) {
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U64 effective_addr2;
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U32 temp = *inst;
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int r1 = (temp >> 20) & 0xf;
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int b2 = (temp >> 16) & 0xf;
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effective_addr2 = temp & 0xfff;
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if (b2) effective_addr2 += regs[b2];
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b2 = (temp >> 12) & 0xf;
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if (b2) effective_addr2 += regs[b2];
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effective_addr2 &= regs[4];
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if ((effective_addr2 & 3) == 0)
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return 1;
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return 0;
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}
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Note that only the low 2 bits of effective_addr2 are used. On 32-bit systems,
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we don't eliminate the computation of the top half of effective_addr2 because
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we don't have whole-function selection dags. On x86, this means we use one
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extra register for the function when effective_addr2 is declared as U64 than
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when it is declared U32.
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//===---------------------------------------------------------------------===//
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Promote for i32 bswap can use i64 bswap + shr. Useful on targets with 64-bit
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regs and bswap, like itanium.
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//===---------------------------------------------------------------------===//
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LSR should know what GPR types a target has. This code:
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volatile short X, Y; // globals
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void foo(int N) {
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int i;
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for (i = 0; i < N; i++) { X = i; Y = i*4; }
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}
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produces two identical IV's (after promotion) on PPC/ARM:
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LBB1_1: @bb.preheader
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mov r3, #0
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mov r2, r3
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mov r1, r3
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LBB1_2: @bb
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ldr r12, LCPI1_0
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ldr r12, [r12]
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strh r2, [r12]
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ldr r12, LCPI1_1
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ldr r12, [r12]
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strh r3, [r12]
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add r1, r1, #1 <- [0,+,1]
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add r3, r3, #4
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add r2, r2, #1 <- [0,+,1]
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cmp r1, r0
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bne LBB1_2 @bb
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//===---------------------------------------------------------------------===//
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Tail call elim should be more aggressive, checking to see if the call is
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followed by an uncond branch to an exit block.
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; This testcase is due to tail-duplication not wanting to copy the return
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; instruction into the terminating blocks because there was other code
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; optimized out of the function after the taildup happened.
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;RUN: llvm-upgrade < %s | llvm-as | opt -tailcallelim | llvm-dis | not grep call
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int %t4(int %a) {
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entry:
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%tmp.1 = and int %a, 1
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%tmp.2 = cast int %tmp.1 to bool
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br bool %tmp.2, label %then.0, label %else.0
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then.0:
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%tmp.5 = add int %a, -1
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%tmp.3 = call int %t4( int %tmp.5 )
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br label %return
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else.0:
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%tmp.7 = setne int %a, 0
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br bool %tmp.7, label %then.1, label %return
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then.1:
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%tmp.11 = add int %a, -2
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%tmp.9 = call int %t4( int %tmp.11 )
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br label %return
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return:
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%result.0 = phi int [ 0, %else.0 ], [ %tmp.3, %then.0 ],
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[ %tmp.9, %then.1 ]
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ret int %result.0
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}
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//===---------------------------------------------------------------------===//
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Tail recursion elimination is not transforming this function, because it is
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returning n, which fails the isDynamicConstant check in the accumulator
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recursion checks.
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long long fib(const long long n) {
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switch(n) {
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case 0:
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case 1:
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return n;
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default:
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return fib(n-1) + fib(n-2);
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}
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}
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//===---------------------------------------------------------------------===//
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Argument promotion should promote arguments for recursive functions, like
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this:
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; RUN: llvm-upgrade < %s | llvm-as | opt -argpromotion | llvm-dis | grep x.val
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implementation ; Functions:
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internal int %foo(int* %x) {
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entry:
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%tmp = load int* %x
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%tmp.foo = call int %foo(int *%x)
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ret int %tmp.foo
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}
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int %bar(int* %x) {
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entry:
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%tmp3 = call int %foo( int* %x) ; <int>[#uses=1]
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ret int %tmp3
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}
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