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34605b3847
This patch tries to reassociate two patterns related to FMA to expose more ILP on PowerPC. // Pattern 1: // A = FADD X, Y (Leaf) // B = FMA A, M21, M22 (Prev) // C = FMA B, M31, M32 (Root) // --> // A = FMA X, M21, M22 // B = FMA Y, M31, M32 // C = FADD A, B // Pattern 2: // A = FMA X, M11, M12 (Leaf) // B = FMA A, M21, M22 (Prev) // C = FMA B, M31, M32 (Root) // --> // A = FMUL M11, M12 // B = FMA X, M21, M22 // D = FMA A, M31, M32 // C = FADD B, D Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D80175
157 lines
3.5 KiB
C++
157 lines
3.5 KiB
C++
//===-- llvm/CodeGen/MachineCombinerPattern.h - Instruction pattern supported by
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// combiner ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines instruction pattern supported by combiner
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINECOMBINERPATTERN_H
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#define LLVM_CODEGEN_MACHINECOMBINERPATTERN_H
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namespace llvm {
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/// These are instruction patterns matched by the machine combiner pass.
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enum class MachineCombinerPattern {
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// These are commutative variants for reassociating a computation chain. See
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// the comments before getMachineCombinerPatterns() in TargetInstrInfo.cpp.
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REASSOC_AX_BY,
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REASSOC_AX_YB,
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REASSOC_XA_BY,
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REASSOC_XA_YB,
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// These are patterns matched by the PowerPC to reassociate FMA chains.
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REASSOC_XY_AMM_BMM,
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REASSOC_XMM_AMM_BMM,
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// These are multiply-add patterns matched by the AArch64 machine combiner.
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MULADDW_OP1,
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MULADDW_OP2,
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MULSUBW_OP1,
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MULSUBW_OP2,
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MULADDWI_OP1,
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MULSUBWI_OP1,
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MULADDX_OP1,
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MULADDX_OP2,
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MULSUBX_OP1,
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MULSUBX_OP2,
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MULADDXI_OP1,
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MULSUBXI_OP1,
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// NEON integers vectors
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MULADDv8i8_OP1,
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MULADDv8i8_OP2,
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MULADDv16i8_OP1,
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MULADDv16i8_OP2,
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MULADDv4i16_OP1,
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MULADDv4i16_OP2,
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MULADDv8i16_OP1,
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MULADDv8i16_OP2,
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MULADDv2i32_OP1,
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MULADDv2i32_OP2,
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MULADDv4i32_OP1,
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MULADDv4i32_OP2,
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MULSUBv8i8_OP1,
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MULSUBv8i8_OP2,
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MULSUBv16i8_OP1,
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MULSUBv16i8_OP2,
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MULSUBv4i16_OP1,
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MULSUBv4i16_OP2,
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MULSUBv8i16_OP1,
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MULSUBv8i16_OP2,
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MULSUBv2i32_OP1,
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MULSUBv2i32_OP2,
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MULSUBv4i32_OP1,
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MULSUBv4i32_OP2,
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MULADDv4i16_indexed_OP1,
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MULADDv4i16_indexed_OP2,
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MULADDv8i16_indexed_OP1,
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MULADDv8i16_indexed_OP2,
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MULADDv2i32_indexed_OP1,
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MULADDv2i32_indexed_OP2,
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MULADDv4i32_indexed_OP1,
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MULADDv4i32_indexed_OP2,
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MULSUBv4i16_indexed_OP1,
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MULSUBv4i16_indexed_OP2,
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MULSUBv8i16_indexed_OP1,
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MULSUBv8i16_indexed_OP2,
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MULSUBv2i32_indexed_OP1,
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MULSUBv2i32_indexed_OP2,
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MULSUBv4i32_indexed_OP1,
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MULSUBv4i32_indexed_OP2,
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// Floating Point
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FMULADDH_OP1,
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FMULADDH_OP2,
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FMULSUBH_OP1,
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FMULSUBH_OP2,
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FMULADDS_OP1,
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FMULADDS_OP2,
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FMULSUBS_OP1,
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FMULSUBS_OP2,
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FMULADDD_OP1,
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FMULADDD_OP2,
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FMULSUBD_OP1,
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FMULSUBD_OP2,
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FNMULSUBH_OP1,
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FNMULSUBS_OP1,
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FNMULSUBD_OP1,
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FMLAv1i32_indexed_OP1,
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FMLAv1i32_indexed_OP2,
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FMLAv1i64_indexed_OP1,
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FMLAv1i64_indexed_OP2,
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FMLAv4f16_OP1,
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FMLAv4f16_OP2,
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FMLAv8f16_OP1,
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FMLAv8f16_OP2,
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FMLAv2f32_OP2,
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FMLAv2f32_OP1,
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FMLAv2f64_OP1,
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FMLAv2f64_OP2,
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FMLAv4i16_indexed_OP1,
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FMLAv4i16_indexed_OP2,
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FMLAv8i16_indexed_OP1,
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FMLAv8i16_indexed_OP2,
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FMLAv2i32_indexed_OP1,
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FMLAv2i32_indexed_OP2,
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FMLAv2i64_indexed_OP1,
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FMLAv2i64_indexed_OP2,
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FMLAv4f32_OP1,
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FMLAv4f32_OP2,
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FMLAv4i32_indexed_OP1,
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FMLAv4i32_indexed_OP2,
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FMLSv1i32_indexed_OP2,
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FMLSv1i64_indexed_OP2,
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FMLSv4f16_OP1,
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FMLSv4f16_OP2,
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FMLSv8f16_OP1,
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FMLSv8f16_OP2,
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FMLSv2f32_OP1,
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FMLSv2f32_OP2,
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FMLSv2f64_OP1,
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FMLSv2f64_OP2,
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FMLSv4i16_indexed_OP1,
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FMLSv4i16_indexed_OP2,
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FMLSv8i16_indexed_OP1,
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FMLSv8i16_indexed_OP2,
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FMLSv2i32_indexed_OP1,
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FMLSv2i32_indexed_OP2,
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FMLSv2i64_indexed_OP1,
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FMLSv2i64_indexed_OP2,
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FMLSv4f32_OP1,
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FMLSv4f32_OP2,
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FMLSv4i32_indexed_OP1,
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FMLSv4i32_indexed_OP2
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};
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} // end namespace llvm
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#endif
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